RDP433 and RDP418 has NAND and eMMC variants. Presently, only NAND
variant is supported. To enable support for eMMC variant, add the
relevant GPIO and regulator information.
Do not enable NAND or eMMC by default in ipq9574-rdp-common.dtsi. Enable
it in board specific DTS as applicable.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260205085936.3220108-2-varadarajan.narayanan@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
stdout-path = "serial0:115200n8";
};
+ regulator_fixed_1p8: s1800 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "fixed_1p8";
+ };
+
regulator_fixed_3p3: s3300 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
};
};
+&sdhc_1 {
+ vmmc-supply = <®ulator_fixed_3p3>;
+ vqmmc-supply = <®ulator_fixed_1p8>;
+};
+
&sleep_clk {
clock-frequency = <32000>;
};
bias-disable;
};
};
+
+ sdc_default_state: sdc-default-state {
+ clk-pins {
+ pins = "gpio5";
+ function = "sdc_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio4";
+ function = "sdc_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3", "gpio6", "gpio7",
+ "gpio8", "gpio9";
+ function = "sdc_data";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "gpio10";
+ function = "sdc_rclk";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
};
&qpic_bam {
pinctrl-0 = <&qpic_snand_default_state>;
pinctrl-names = "default";
- status = "okay";
-
flash@0 {
compatible = "spi-nand";
reg = <0>;
};
-&sdhc_1 {
- pinctrl-0 = <&sdc_default_state>;
- pinctrl-names = "default";
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe;
- max-frequency = <384000000>;
- bus-width = <8>;
+&qpic_nand {
status = "okay";
};
-
-&tlmm {
- sdc_default_state: sdc-default-state {
- clk-pins {
- pins = "gpio5";
- function = "sdc_clk";
- drive-strength = <8>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "gpio4";
- function = "sdc_cmd";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "gpio0", "gpio1", "gpio2",
- "gpio3", "gpio6", "gpio7",
- "gpio8", "gpio9";
- function = "sdc_data";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- rclk-pins {
- pins = "gpio10";
- function = "sdc_rclk";
- drive-strength = <8>;
- bias-pull-down;
- };
- };
-};
status = "okay";
};
+&qpic_nand {
+ status = "okay";
+};
+
&tlmm {
pcie1_default: pcie1-default-state {
compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
};
+
+&qpic_nand {
+ status = "okay";
+};
compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
};
+
+&qpic_nand {
+ status = "okay";
+};
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
};
+
+&qpic_nand {
+ status = "okay";
+};
clock-names = "iface", "core", "xo", "ice";
non-removable;
supports-cqe;
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ max-frequency = <384000000>;
+ bus-width = <8>;
+
status = "disabled";
};