soc: mediatek: mt8167-mmsys: Fix missing regval in all entries

The mmsys routing table for this SoC was effectively missing
initialization of the val variable of struct mtk_mmsys_routes:
this means that `val` was incorrectly initialized to zero,
hence the registers were wrongly initialized.

Add the required regval to all of the entries of the routing
table for this SoC to fix display controller functionality.

Fixes: 060f7875bd23 ("soc: mediatek: mmsys: Add support for MT8167 SoC")
Link: https://lore.kernel.org/r/20250212100012.33001-6-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index f7a35b3656bb135c57f3f99ec6cb3a70b82cf164..655ef962abe9f416e1e809f8da25dfaf58de5392 100644 (file)
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -17,18 +17,23 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
        {
                DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
                MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
+               OVL0_MOUT_EN_COLOR0
        }, {
                DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
-               MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
+               MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
+               MT8167_DITHER_MOUT_EN_RDMA0
        }, {
                DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
-               MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0
+               MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
+               COLOR0_SEL_IN_OVL0
        }, {
                DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
-               MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0
+               MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
+               MT8167_DSI0_SEL_IN_RDMA0
        }, {
                DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
-               MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0
+               MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
+               MT8167_RDMA0_SOUT_DSI0
        },
 };