drm/amd/pm: force send pcie parmater on navi1x

[ Upstream commit dc8a887de1a7d397ab4131f45676e89565417aa8 ]

v1:
the PMFW didn't initialize the PCIe DPM parameters
and requires the KMD to actively provide these parameters.

v2:
clean & remove unused code logic (lijo)

Fixes: 1a18607c07bb ("drm/amd/pm: override pcie dpm parameters only if it is necessary")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4671
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit b0dbd5db7cf1f81e4aaedd25cb5e72ce369387b2)
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index d0fd9537e62365fcec6ca3ca9f80f8ae0d3f80b7..a2fcf678182b4e3738210cb3329f086115f1f0fc 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2454,24 +2454,21 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
        }
 
        for (i = 0; i < NUM_LINK_LEVELS; i++) {
-               if (pptable->PcieGenSpeed[i] > pcie_gen_cap ||
-                       pptable->PcieLaneCount[i] > pcie_width_cap) {
-                       dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
-                                                                       pptable->PcieGenSpeed[i] > pcie_gen_cap ?
-                                                                       pcie_gen_cap : pptable->PcieGenSpeed[i];
-                       dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
-                                                                       pptable->PcieLaneCount[i] > pcie_width_cap ?
-                                                                       pcie_width_cap : pptable->PcieLaneCount[i];
-                       smu_pcie_arg = i << 16;
-                       smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_gen[i] << 8;
-                       smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_lane[i];
-                       ret = smu_cmn_send_smc_msg_with_param(smu,
-                                                       SMU_MSG_OverridePcieParameters,
-                                                       smu_pcie_arg,
-                                                       NULL);
-                       if (ret)
-                               break;
-               }
+               dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
+                       pptable->PcieGenSpeed[i] > pcie_gen_cap ?
+                       pcie_gen_cap : pptable->PcieGenSpeed[i];
+               dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
+                       pptable->PcieLaneCount[i] > pcie_width_cap ?
+                       pcie_width_cap : pptable->PcieLaneCount[i];
+               smu_pcie_arg = i << 16;
+               smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_gen[i] << 8;
+               smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_lane[i];
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                     SMU_MSG_OverridePcieParameters,
+                                                     smu_pcie_arg,
+                                                     NULL);
+               if (ret)
+                       return ret;
        }
 
        return ret;