The msr_hcr_el2 macro is slightly awkward, as it provides an ISB
when CONFIG_AMPERE_ERRATUM_AC04_CPU_23 is present, and none
otherwise. Note that this this option is 'default y', meaning that
it is likely to be selected.
Most instances of msr_hcr_el2 are also immediately followed by an ISB,
meaning that in most cases, you end-up with two back-to-back ISBs.
This isn't a big deal, but once you have seen that, you can't unsee it.
Rework the msr_hcr_el2 macro to always provide the ISB, and drop
the superfluous ISBs everywhere else.
Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Link: https://patch.msgid.link/20260321212419.2803972-6-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
* effectively VHE-only or not.
*/
msr_hcr_el2 x0 // Setup HCR_EL2 as nVHE
- isb
mov x1, #1 // Write something to FAR_EL1
msr far_el1, x1
isb
.LnE2H0_\@:
orr x0, x0, #HCR_E2H
msr_hcr_el2 x0
- isb
.LnVHE_\@:
.endm
.macro msr_hcr_el2, reg
#if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23)
dsb nsh
- msr hcr_el2, \reg
- isb
-#else
- msr hcr_el2, \reg
#endif
+ msr hcr_el2, \reg
+ isb // Required by AMPERE_ERRATUM_AC04_CPU_23
.endm
#else
// Engage the VHE magic!
mov_q x0, HCR_HOST_VHE_FLAGS
msr_hcr_el2 x0
- isb
// Use the EL1 allocated stack, per-cpu offset
mrs x0, sp_el1
mrs x0, hcr_el2
bic x0, x0, #HCR_VM
msr_hcr_el2 x0
- isb
tlbi vmalls12e1
dsb nsh
#endif