]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amd/ras: Compatible with legacy sriov host
authorYiPeng Chai <YiPeng.Chai@amd.com>
Mon, 3 Nov 2025 08:32:18 +0000 (16:32 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 8 Dec 2025 18:56:34 +0000 (13:56 -0500)
If sriov host is legacy, the guest uniras will
be disabled.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h

index 2d48818773c0c0163369ae16cf319f7f25b80ee0..759f3c642331d2cfeb2d1f74f59d3d475c000076 100644 (file)
@@ -37,6 +37,7 @@
 #include "vi.h"
 #include "soc15.h"
 #include "nv.h"
+#include "amdgpu_virt_ras_cmd.h"
 
 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
        do { \
@@ -1533,6 +1534,9 @@ bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev)
        if (adev->virt.ras_en_caps.bits.poison_propogation_mode)
                con->poison_supported = true; /* Poison is handled by host */
 
+       if (adev->virt.ras_en_caps.bits.uniras_supported)
+               amdgpu_virt_ras_set_remote_uniras(adev, true);
+
        return true;
 }
 
index 3cdb1e0eca377959758bed1bf38200388a1d56df..cffb2f805de24e9ed419b5f78fe1fec6f3d4cbbb 100644 (file)
@@ -201,7 +201,8 @@ union amd_sriov_ras_caps {
                uint64_t block_mpio                     : 1;
                uint64_t block_mmsch                    : 1;
                uint64_t poison_propogation_mode        : 1;
-               uint64_t reserved                       : 43;
+               uint64_t uniras_supported               : 1;
+               uint64_t reserved                       : 42;
        } bits;
        uint64_t all;
 };
index cb7fbc791c3cf5978a6f16bb4e8f27f4dadc93dd..923bddd0af3a28bce0a345c319d9ed2112bc4e4a 100644 (file)
@@ -452,6 +452,9 @@ bool amdgpu_uniras_enabled(struct amdgpu_device *adev)
 {
        struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
 
+       if (amdgpu_sriov_vf(adev))
+               return amdgpu_virt_ras_remote_uniras_enabled(adev);
+
        if (!ras_mgr || !ras_mgr->ras_core)
                return false;
 
index 895b68785849c349251a52356fb196990595fad6..5e90a187155b31a77aa1163b956cbdee75634d0a 100644 (file)
@@ -380,6 +380,8 @@ int amdgpu_virt_ras_hw_init(struct amdgpu_device *adev)
                        (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd;
        struct vram_blocks_ecc *blks_ecc = &virt_ras->blocks_ecc;
 
+       amdgpu_virt_get_ras_capability(adev);
+
        memset(blks_ecc, 0, sizeof(*blks_ecc));
        blks_ecc->size = PAGE_SIZE;
        if (amdgpu_bo_create_kernel(adev, blks_ecc->size,
@@ -428,3 +430,31 @@ int amdgpu_virt_ras_post_reset(struct amdgpu_device *adev)
 {
        return 0;
 }
+
+void amdgpu_virt_ras_set_remote_uniras(struct amdgpu_device *adev, bool en)
+{
+       struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
+       struct amdgpu_virt_ras_cmd *virt_ras;
+
+       if (!ras_mgr || !ras_mgr->virt_ras_cmd)
+               return;
+
+       virt_ras = (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd;
+       virt_ras->remote_uniras_supported = en;
+}
+
+bool amdgpu_virt_ras_remote_uniras_enabled(struct amdgpu_device *adev)
+{
+       struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
+       struct amdgpu_virt_ras_cmd *virt_ras;
+
+       if (amdgpu_in_reset(adev))
+               return false;
+
+       if (!ras_mgr || !ras_mgr->virt_ras_cmd)
+               return false;
+
+       virt_ras = (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd;
+
+       return virt_ras->remote_uniras_supported;
+}
index 03c3cf8363ca495cd798e0bdafd26fa8d66b50d7..53b0f3f60103e76008df5ed235249e0c105db19a 100644 (file)
@@ -39,6 +39,7 @@ struct vram_blocks_ecc {
 };
 
 struct amdgpu_virt_ras_cmd {
+       bool remote_uniras_supported;
        struct remote_batch_trace_mgr batch_mgr;
        struct vram_blocks_ecc blocks_ecc;
 };
@@ -51,4 +52,6 @@ int amdgpu_virt_ras_handle_cmd(struct ras_core_context *ras_core,
                struct ras_cmd_ctx *cmd);
 int amdgpu_virt_ras_pre_reset(struct amdgpu_device *adev);
 int amdgpu_virt_ras_post_reset(struct amdgpu_device *adev);
+void amdgpu_virt_ras_set_remote_uniras(struct amdgpu_device *adev, bool en);
+bool amdgpu_virt_ras_remote_uniras_enabled(struct amdgpu_device *adev);
 #endif