]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
wifi: rtw89: 8922d: add ops related to BT coexistence mechanism
authorPing-Ke Shih <pkshih@realtek.com>
Mon, 30 Mar 2026 06:58:45 +0000 (14:58 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Thu, 2 Apr 2026 03:20:07 +0000 (11:20 +0800)
The ops is used by shared BT coexistence mechanism to set WiFi TX power,
get BT RSSI, and TX/RX parameters.

The RTL8922D uses TX/RX parameter v9, so define it and fill NULL for
other chips.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260330065847.48946-8-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/rtw8851b.c
drivers/net/wireless/realtek/rtw89/rtw8852a.c
drivers/net/wireless/realtek/rtw89/rtw8852b.c
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
drivers/net/wireless/realtek/rtw89/rtw8852c.c
drivers/net/wireless/realtek/rtw89/rtw8922a.c
drivers/net/wireless/realtek/rtw89/rtw8922d.c

index 4b4d25d8ba98d67575b56cab58be05b2dfc42c2b..fd29dbbb120d2f77a749d4b571fa8b0d04c69926 100644 (file)
@@ -873,6 +873,14 @@ enum rtw89_phy_idx {
        RTW89_PHY_NUM,
 };
 
+enum rtw89_fbtc_bt_index {
+       BTC_BT_1ST = 0x0,
+       BTC_BT_2ND = 0x1,
+       BTC_BT_EXT = 0x2,
+       BTC_ALL_BT = 0x2,
+       BTC_ALL_BT_EZL = 0x3 /* BT0+BT1+Ext-ZB(or Thread, or LTE) */
+};
+
 #define __RTW89_MLD_MAX_LINK_NUM 2
 #define RTW89_MLD_NON_STA_LINK_NUM 1
 
@@ -2197,6 +2205,15 @@ struct rtw89_btc_bt_info {
        u32 rsvd: 17;
 };
 
+struct rtw89_btc_rf_trx_para_v9 {
+       u32 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 1's complement -5->0x85 */
+       u32 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */
+       u32 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */
+       u32 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */
+       u32 zb_tx_power[BTC_ALL_BT]; /* 15.4 devrease Tx power (dB) */
+       u32 zb_rx_gain[BTC_ALL_BT]; /* 15.4 constrain level */
+};
+
 struct rtw89_btc_cx {
        struct rtw89_btc_wl_info wl;
        struct rtw89_btc_bt_info bt;
@@ -4609,6 +4626,10 @@ struct rtw89_chip_info {
        const struct rtw89_btc_rf_trx_para *rf_para_ulink;
        u8 rf_para_dlink_num;
        const struct rtw89_btc_rf_trx_para *rf_para_dlink;
+       const struct rtw89_btc_rf_trx_para_v9 *rf_para_ulink_v9;
+       const struct rtw89_btc_rf_trx_para_v9 *rf_para_dlink_v9;
+       u8 rf_para_ulink_num_v9;
+       u8 rf_para_dlink_num_v9;
        u8 ps_mode_supported;
        u8 low_power_hci_modes;
 
index 2005934f64d260e30b49d02c3b3378067fb065d1..84bdd39b3cebc361f879866986c85a1de8e4ea27 100644 (file)
@@ -2681,6 +2681,10 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
        .rf_para_ulink          = rtw89_btc_8851b_rf_ul,
        .rf_para_dlink_num      = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
        .rf_para_dlink          = rtw89_btc_8851b_rf_dl,
+       .rf_para_ulink_v9       = NULL,
+       .rf_para_dlink_v9       = NULL,
+       .rf_para_ulink_num_v9   = 0,
+       .rf_para_dlink_num_v9   = 0,
        .ps_mode_supported      = BIT(RTW89_PS_MODE_RFOFF) |
                                  BIT(RTW89_PS_MODE_CLK_GATED),
        .low_power_hci_modes    = 0,
index 12ed35f548c115ed2426a46837caa14bcbd41812..1d4f1df524a1cd8982b5493df1920ae3c05d72c4 100644 (file)
@@ -2418,6 +2418,10 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
        .rf_para_ulink          = rtw89_btc_8852a_rf_ul,
        .rf_para_dlink_num      = ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
        .rf_para_dlink          = rtw89_btc_8852a_rf_dl,
+       .rf_para_ulink_v9       = NULL,
+       .rf_para_dlink_v9       = NULL,
+       .rf_para_ulink_num_v9   = 0,
+       .rf_para_dlink_num_v9   = 0,
        .ps_mode_supported      = BIT(RTW89_PS_MODE_RFOFF) |
                                  BIT(RTW89_PS_MODE_CLK_GATED) |
                                  BIT(RTW89_PS_MODE_PWR_GATED),
index dcb15f26c1b19e050632e65ee1054745542045ba..5e8738bb2dc2ebfadb375af881c82295f7baefdc 100644 (file)
@@ -1014,6 +1014,10 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
        .rf_para_ulink          = rtw89_btc_8852b_rf_ul,
        .rf_para_dlink_num      = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
        .rf_para_dlink          = rtw89_btc_8852b_rf_dl,
+       .rf_para_ulink_v9       = NULL,
+       .rf_para_dlink_v9       = NULL,
+       .rf_para_ulink_num_v9   = 0,
+       .rf_para_dlink_num_v9   = 0,
        .ps_mode_supported      = BIT(RTW89_PS_MODE_RFOFF) |
                                  BIT(RTW89_PS_MODE_CLK_GATED) |
                                  BIT(RTW89_PS_MODE_PWR_GATED),
index 2afc6908cc7e3da79a38b9230bbca3f5ff1ea393..ab4263bc8b9f375004dd58a24893ad2cabf046c7 100644 (file)
@@ -853,6 +853,10 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
        .rf_para_ulink          = rtw89_btc_8852bt_rf_ul,
        .rf_para_dlink_num      = ARRAY_SIZE(rtw89_btc_8852bt_rf_dl),
        .rf_para_dlink          = rtw89_btc_8852bt_rf_dl,
+       .rf_para_ulink_v9       = NULL,
+       .rf_para_dlink_v9       = NULL,
+       .rf_para_ulink_num_v9   = 0,
+       .rf_para_dlink_num_v9   = 0,
        .ps_mode_supported      = BIT(RTW89_PS_MODE_RFOFF) |
                                  BIT(RTW89_PS_MODE_CLK_GATED) |
                                  BIT(RTW89_PS_MODE_PWR_GATED),
index 5f9da0f85bb5287f839cde68e0a63e420aca6d95..40db7e3c0d9740fa8bbfa2ee15e9d44cd18e8e77 100644 (file)
@@ -3211,6 +3211,10 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
        .rf_para_ulink          = rtw89_btc_8852c_rf_ul,
        .rf_para_dlink_num      = ARRAY_SIZE(rtw89_btc_8852c_rf_dl),
        .rf_para_dlink          = rtw89_btc_8852c_rf_dl,
+       .rf_para_ulink_v9       = NULL,
+       .rf_para_dlink_v9       = NULL,
+       .rf_para_ulink_num_v9   = 0,
+       .rf_para_dlink_num_v9   = 0,
        .ps_mode_supported      = BIT(RTW89_PS_MODE_RFOFF) |
                                  BIT(RTW89_PS_MODE_CLK_GATED) |
                                  BIT(RTW89_PS_MODE_PWR_GATED),
index 5f83e71ed2184740ca05e59b1b3f67b02228bd31..8f6cf64271e891deb91a327d60381331562e1c64 100644 (file)
@@ -3015,6 +3015,10 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
        .rf_para_ulink          = rtw89_btc_8922a_rf_ul,
        .rf_para_dlink_num      = ARRAY_SIZE(rtw89_btc_8922a_rf_dl),
        .rf_para_dlink          = rtw89_btc_8922a_rf_dl,
+       .rf_para_ulink_v9       = NULL,
+       .rf_para_dlink_v9       = NULL,
+       .rf_para_ulink_num_v9   = 0,
+       .rf_para_dlink_num_v9   = 0,
        .ps_mode_supported      = BIT(RTW89_PS_MODE_RFOFF) |
                                  BIT(RTW89_PS_MODE_CLK_GATED) |
                                  BIT(RTW89_PS_MODE_PWR_GATED),
index 49b84d49ccace29c71e228802cade0db51d15aa8..a9a7ffb5fb587a18c5a44ddd2c9aa79402fdbb89 100644 (file)
@@ -2619,6 +2619,129 @@ static u32 rtw8922d_chan_to_rf18_val(struct rtw89_dev *rtwdev,
        return val;
 }
 
+static void rtw8922d_btc_set_rfe(struct rtw89_dev *rtwdev)
+{
+}
+
+static void rtw8922d_btc_init_cfg(struct rtw89_dev *rtwdev)
+{
+       /* offload to firmware */
+}
+
+static void
+rtw8922d_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
+{
+       u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));
+       u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));
+
+       switch (ctrl_all_time) {
+       case 0xffff:
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
+                                            B_BE_FORCE_PWR_BY_RATE_EN, 0x0);
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
+                                            B_BE_FORCE_PWR_BY_RATE_VAL, 0x0);
+               break;
+       default:
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
+                                            B_BE_FORCE_PWR_BY_RATE_VAL, ctrl_all_time);
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
+                                            B_BE_FORCE_PWR_BY_RATE_EN, 0x1);
+               break;
+       }
+
+       switch (ctrl_gnt_bt) {
+       case 0xffff:
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
+                                            B_BE_PWR_BT_EN, 0x0);
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
+                                            B_BE_PWR_BT_VAL, 0x0);
+               break;
+       default:
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
+                                            B_BE_PWR_BT_VAL, ctrl_gnt_bt);
+               rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
+                                            B_BE_PWR_BT_EN, 0x1);
+               break;
+       }
+}
+
+static
+s8 rtw8922d_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
+{
+       return clamp_t(s8, val, -100, 0) + 100;
+}
+
+static const struct rtw89_btc_rf_trx_para_v9 rtw89_btc_8922d_rf_ul_v9[] = {
+       /*
+        * 0 -> original
+        * 1 -> for BT-connected ACI issue && BTG co-rx
+        * 2 ~ 4 ->reserved for shared-antenna
+        * 5 ~ 8 ->for non-shared-antenna free-run
+        */
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {2, 2}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{ 6,  6}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{13, 13}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{13, 13}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+};
+
+static const struct rtw89_btc_rf_trx_para_v9 rtw89_btc_8922d_rf_dl_v9[] = {
+       /*
+        * 0 -> original
+        * 1 -> for BT-connected ACI issue && BTG co-rx
+        * 2 ~ 4 ->reserved for shared-antenna
+        * 5 ~ 8 ->for non-shared-antenna free-run
+        */
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {2, 2}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {0, 0}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+       {{15, 15}, {1, 1}, {0, 0}, {7, 7}, {0, 0}, {0, 0}},
+};
+
+static const u8 rtw89_btc_8922d_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
+static const u8 rtw89_btc_8922d_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
+
+static const struct rtw89_btc_fbtc_mreg rtw89_btc_8922d_mon_reg[] = {
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe354),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe35c),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe370),
+       RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe380),
+};
+
+static
+void rtw8922d_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
+{
+       /* Feature move to firmware */
+}
+
+static
+void rtw8922d_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
+{
+       /* Feature move to firmware */
+}
+
+static void rtw8922d_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
+{
+       /* Feature move to firmware */
+}
+
 MODULE_FIRMWARE(RTW8922D_MODULE_FIRMWARE);
 MODULE_FIRMWARE(RTW8922DS_MODULE_FIRMWARE);
 MODULE_AUTHOR("Realtek Corporation");