drm/i915/vrr: Enable DC Balance

Enable DC Balance from vrr compute config and related hw flag.
Also to add pipe restrictions along with this.

--v2:
- Use dc balance check instead of source restriction.
--v3:
- Club pipe restriction check with dc balance enablement. (Ankit)
--v4:
- Separate out Pipe restrictions to patch#7

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-19-mitulkumar.ajitkumar.golani@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1522ec3a98b8fef7b5f961d0d6bec5b9c2b386d2..db74744ddb31a927bbabcbb8ed3923de055b7c2f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
        crtc_state->vrr.dc_balance.vblank_target =
                DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
                             DCB_BLANK_TARGET, 100);
+       crtc_state->vrr.dc_balance.enable = true;
 }
 
 void
@@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        enum pipe pipe = crtc->pipe;
+       u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
        if (!crtc_state->vrr.dc_balance.enable)
                return;
@@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
        intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
                       ADAPTIVE_SYNC_COUNTER_EN);
        intel_pipedmc_dcb_enable(NULL, crtc);
+
+       vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
+       intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void
@@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
        enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
        enum pipe pipe = crtc->pipe;
+       u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
 
        if (!old_crtc_state->vrr.dc_balance.enable)
                return;
@@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
        intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
        intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
        intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+
+       vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
+       intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,