]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
cxl/decoder: Drop pointless locking
authorDan Williams <dan.j.williams@intel.com>
Fri, 11 Jul 2025 23:49:28 +0000 (16:49 -0700)
committerDave Jiang <dave.jiang@intel.com>
Wed, 16 Jul 2025 18:34:36 +0000 (11:34 -0700)
cxl_dpa_rwsem coordinates changes to dpa allocation settings for a given
decoder. cxl_decoder_reset() has no need for a consistent snapshot of the
dpa settings since it is merely clearing out whatever was there previously.

Otherwise, cxl_region_rwsem protects against 'reset' racing 'setup'.

In preparation for converting to rw_semaphore_acquire semantics, drop this
locking.

Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20250711234932.671292-5-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/hdm.c

index 81556d12e9b8b1194ece0ebace16fef074725143..e9cb34e302486c0ad54ed7a369b8ec60123333f5 100644 (file)
@@ -914,7 +914,6 @@ static void cxl_decoder_reset(struct cxl_decoder *cxld)
                        "%s: out of order reset, expected decoder%d.%d\n",
                        dev_name(&cxld->dev), port->id, port->commit_end);
 
-       down_read(&cxl_dpa_rwsem);
        ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
        ctrl &= ~CXL_HDM_DECODER0_CTRL_COMMIT;
        writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
@@ -923,7 +922,6 @@ static void cxl_decoder_reset(struct cxl_decoder *cxld)
        writel(0, hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id));
        writel(0, hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
        writel(0, hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
-       up_read(&cxl_dpa_rwsem);
 
        cxld->flags &= ~CXL_DECODER_F_ENABLE;