};
ospi: spi@f1010000 {
- compatible = "cdns,qspi-nor";
+ compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor";
status = "okay";
reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
clock-names = "ref_clk", "pclk";
num-cs = <1>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
- cdns,is-dma = <1>;
cdns,is-stig-pgm = <1>;
cdns,trigger-address = <0xc0000000>;
#address-cells = <1>;
/* Quirks */
#define CQSPI_DISABLE_STIG_MODE BIT(0)
+#define CQSPI_DMA_MODE BIT(1)
__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
const struct spi_mem_op *op)
priv->regbase = plat->regbase;
priv->ahbbase = plat->ahbbase;
- priv->is_dma = plat->is_dma;
priv->is_decoded_cs = plat->is_decoded_cs;
priv->fifo_depth = plat->fifo_depth;
priv->fifo_width = plat->fifo_width;
priv->tslch_ns = plat->tslch_ns;
priv->quirks = plat->quirks;
+ if (priv->quirks & CQSPI_DMA_MODE) {
+ priv->is_dma = true;
+ debug("Cadence QSPI: DMA mode enabled\n");
+ }
+
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
if (plat->ahbsize >= SZ_8M)
priv->use_dac_mode = true;
- plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
-
/* All other parameters are embedded in the child node */
subnode = cadence_qspi_get_subnode(bus);
if (!ofnode_valid(subnode)) {
.quirks = CQSPI_DISABLE_STIG_MODE,
};
+static const struct cqspi_driver_platdata cdns_xilinx_qspi = {
+ .quirks = CQSPI_DMA_MODE,
+};
+
static const struct udevice_id cadence_spi_ids[] = {
{
.compatible = "cdns,qspi-nor",
.compatible = "ti,am654-ospi"
},
{
- .compatible = "amd,versal2-ospi"
+ .compatible = "amd,versal2-ospi",
+ .data = (ulong)&cdns_xilinx_qspi,
+ },
+ {
+ .compatible = "xlnx,versal-ospi-1.0",
+ .data = (ulong)&cdns_xilinx_qspi,
},
{ }
};