drm/msm/a6xx: Get a handle to the common UBWC config

Start the great despaghettification by getting a pointer to the common
UBWC configuration, which houses e.g. UBWC versions that we need to
make decisions.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660965/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 5e115abe769216f3b0d196d3686d3c9c4a1c2bb4..26048938470851d1a6480794a66317455bf3b7f4 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -604,8 +604,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
        gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
 }
 
-static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
+static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 {
+       /* Inherit the common config and make some necessary fixups */
+       gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
+       if (IS_ERR(gpu->common_ubwc_cfg))
+               return PTR_ERR(gpu->common_ubwc_cfg);
+
        gpu->ubwc_config.rgb565_predicator = 0;
        gpu->ubwc_config.uavflagprd_inv = 0;
        gpu->ubwc_config.min_acc_len = 0;
@@ -682,6 +687,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
                gpu->ubwc_config.highest_bank_bit = 14;
                gpu->ubwc_config.min_acc_len = 1;
        }
+
+       return 0;
 }
 
 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
@@ -2563,7 +2570,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
        msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
                                  a6xx_fault_handler);
 
-       a6xx_calc_ubwc_config(adreno_gpu);
+       ret = a6xx_calc_ubwc_config(adreno_gpu);
+       if (ret) {
+               a6xx_destroy(&(a6xx_gpu->base.base));
+               return ERR_PTR(ret);
+       }
+
        /* Set up the preemption specific bits and pieces for each ringbuffer */
        a6xx_preempt_init(gpu);
 

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 8650bbd8698e9ab6e31a9ab9ca7ac44c31f337f1..3fc7bb45d28b45131c376924d48cff81ccfa4663 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -12,6 +12,8 @@
 #include <linux/firmware.h>
 #include <linux/iopoll.h>
 
+#include <linux/soc/qcom/ubwc.h>
+
 #include "msm_gpu.h"
 
 #include "adreno_common.xml.h"
@@ -242,6 +244,7 @@ struct adreno_gpu {
                 */
                u32 macrotile_mode;
        } ubwc_config;
+       const struct qcom_ubwc_cfg_data *common_ubwc_cfg;
 
        /*
         * Register offsets are different between some GPUs.