media: rzv2h-ivc: Fix FM_STOP register write

Bit 20 should be written in this register to stop frame processing.
So fix that, as well as the poll condition.

Cc: stable@vger.kernel.org
Fixes: f0b3984d821b ("media: platform: Add Renesas Input Video Control block driver")
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
index d894a880c33f7a5cab5d121ebb3378112ca47a4f..9b75e4b10e99c7eee12b5067283db4f45032290d 100644 (file)
--- a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
+++ b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
@@ -297,9 +297,10 @@ static void rzv2h_ivc_stop_streaming(struct vb2_queue *q)
        struct rzv2h_ivc *ivc = vb2_get_drv_priv(q);
        u32 val = 0;
 
-       rzv2h_ivc_write(ivc, RZV2H_IVC_REG_FM_STOP, 0x1);
+       rzv2h_ivc_write(ivc, RZV2H_IVC_REG_FM_STOP, RZV2H_IVC_REG_FM_STOP_FSTOP);
        readl_poll_timeout(ivc->base + RZV2H_IVC_REG_FM_STOP,
-                          val, !val, 10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
+                          val, !(val & RZV2H_IVC_REG_FM_STOP_FSTOP),
+                          10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
 
        rzv2h_ivc_return_buffers(ivc, VB2_BUF_STATE_ERROR);
        video_device_pipeline_stop(&ivc->vdev.dev);

diff --git a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
index 54c70de31c1eecdb89ff35722b4addf8e0cc2d42..049f223200e395963aab013631b9b797c1be7362 100644 (file)
--- a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
+++ b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
@@ -46,6 +46,7 @@
 #define RZV2H_IVC_REG_FM_MCON                          0x0104
 #define RZV2H_IVC_REG_FM_FRCON                         0x0108
 #define RZV2H_IVC_REG_FM_STOP                          0x010c
+#define RZV2H_IVC_REG_FM_STOP_FSTOP                    BIT(20)
 #define RZV2H_IVC_REG_FM_INT_EN                                0x0120
 #define RZV2H_IVC_VVAL_IFPE                            BIT(0)
 #define RZV2H_IVC_REG_FM_INT_STA                       0x0124