x86/apic: Drop AMD Extended Interrupt LVT macros

AMD defines Extended Interrupt Local Vector Table (EILVT) registers to allow
for additional interrupt sources. While the APIC registers for those are
unique to AMD, the format of those registers follows the standard LVT
registers. Drop EILVT-specific macros in favor of the standard APIC
LVT macros.

Drop unused APIC_EILVT_NR_AMD_K8 and APIC_EILVT_LVTOFF while at it.

No functional change.

  [ bp: Merge the two cleanup patches into one. ]

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Manali Shukla <manali.shukla@amd.com>
Link: https://patch.msgid.link/b98d69037c0102d2ccd082a941888a689cd214c9.1775019269.git.naveen@kernel.org

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index aca89f23d2e002867e8560b2440e66a4e7d6faa4..f3a16eb5a58e7ffdb55f67b221226d96895dcf3b 100644 (file)
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -1545,7 +1545,7 @@ EXPORT_SYMBOL(get_ibs_caps);
 
 static inline int get_eilvt(int offset)
 {
-       return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
+       return !setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 1);
 }
 
 static inline int put_eilvt(int offset)
@@ -1694,7 +1694,7 @@ static void setup_APIC_ibs(void)
        if (offset < 0)
                goto failed;
 
-       if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
+       if (!setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 0))
                return;
 failed:
        pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
@@ -1707,7 +1707,7 @@ static void clear_APIC_ibs(void)
 
        offset = get_ibs_lvt_offset();
        if (offset >= 0)
-               setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
+               setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_FIXED, 1);
 }
 
 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)

diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index be39a543fbe5d06334da4904375f0a3a1958d789..bc125c4429dcd1213b86ffef9419f3252cf9253f 100644 (file)
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -138,15 +138,8 @@
 #define APIC_SEOI      0x420
 #define APIC_IER       0x480
 #define APIC_EILVTn(n) (0x500 + 0x10 * n)
-#define                APIC_EILVT_NR_AMD_K8    1       /* # of extended interrupts */
 #define                APIC_EILVT_NR_AMD_10H   4
 #define                APIC_EILVT_NR_MAX       APIC_EILVT_NR_AMD_10H
-#define                APIC_EILVT_LVTOFF(x)    (((x) >> 4) & 0xF)
-#define                APIC_EILVT_MSG_FIX      0x0
-#define                APIC_EILVT_MSG_SMI      0x2
-#define                APIC_EILVT_MSG_NMI      0x4
-#define                APIC_EILVT_MSG_EXT      0x7
-#define                APIC_EILVT_MASKED       (1 << 16)
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define APIC_BASE_MSR          0x800

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index d93f87f29d03b447b75ae7eb51faaad70e12f04d..eb2d8256f7bbf6d207838370efa1fd0e3878a29c 100644 (file)
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -332,7 +332,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  * Since the offsets must be consistent for all cores, we keep track
  * of the LVT offsets in software and reserve the offset for the same
  * vector also to be used on other cores. An offset is freed by
- * setting the entry to APIC_EILVT_MASKED.
+ * setting the entry to APIC_LVT_MASKED.
  *
  * If the BIOS is right, there should be no conflicts. Otherwise a
  * "[Firmware Bug]: ..." error message is generated. However, if
@@ -344,9 +344,9 @@ static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 {
-       return (old & APIC_EILVT_MASKED)
-               || (new == APIC_EILVT_MASKED)
-               || ((new & ~APIC_EILVT_MASKED) == old);
+       return (old & APIC_LVT_MASKED)
+               || (new == APIC_LVT_MASKED)
+               || ((new & ~APIC_LVT_MASKED) == old);
 }
 
 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
@@ -358,13 +358,13 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
 
        rsvd = atomic_read(&eilvt_offsets[offset]);
        do {
-               vector = rsvd & ~APIC_EILVT_MASKED;     /* 0: unassigned */
+               vector = rsvd & ~APIC_LVT_MASKED;       /* 0: unassigned */
                if (vector && !eilvt_entry_is_changeable(vector, new))
                        /* may not change if vectors are different */
                        return rsvd;
        } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
 
-       rsvd = new & ~APIC_EILVT_MASKED;
+       rsvd = new & ~APIC_LVT_MASKED;
        if (rsvd && rsvd != vector)
                pr_info("LVT offset %d assigned for vector 0x%02x\n",
                        offset, rsvd);

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index da13c1e37f87a9272f818ee93ac216978e041819..3a689d389026accc777d2ef57815b438aa42d062 100644 (file)
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -521,7 +521,7 @@ static void mce_threshold_block_init(struct threshold_block *b, int offset)
 static int setup_APIC_mce_threshold(int reserved, int new)
 {
        if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
-                                             APIC_EILVT_MSG_FIX, 0))
+                                             APIC_DELIVERY_MODE_FIXED, 0))
                return new;
 
        return reserved;
@@ -704,11 +704,11 @@ static void smca_enable_interrupt_vectors(void)
                return;
 
        offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12;
-       if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0))
+       if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
                data->thr_intr_en = 1;
 
        offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4;
-       if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0))
+       if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
                data->dfr_intr_en = 1;
 }