arc: Use correct input operand for *extvsi_n_0 define_insn_and_split

Correct the split condition of the instruction to happen after
reload. Relax operand 1 constrain too.

gcc/ChangeLog:

	* config/arc/arc.md: Modify define_insn_and_split "*extvsi_n_0"

gcc/testsuite/ChangeLog:

	* gcc.target/arc/extvsi-3.c: New test.

Co-authored-by: Michiel Derhaeg <michiel@synopsys.com>
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 8f7e5373fdf1fccbfee495c6c2586c17a0865077..55be6ce74da736a28f9c2092571c17d7ff881947 100644 (file)
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6286,15 +6286,15 @@ archs4x, archs4xd"
 
 (define_insn_and_split "*extvsi_n_0"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (sign_extract:SI (match_operand:SI 1 "register_operand" "0")
+       (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
                         (match_operand:QI 2 "const_int_operand")
                         (const_int 0)))]
   "!TARGET_BARREL_SHIFTER
    && IN_RANGE (INTVAL (operands[2]), 2,
                (optimize_insn_for_size_p () ? 28 : 30))"
   "#"
-  "&& 1"
-[(set (match_dup 0) (and:SI (match_dup 0) (match_dup 3)))
+  "&& reload_completed"
+[(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
  (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))
  (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 4)))]
 {

diff --git a/gcc/testsuite/gcc.target/arc/extvsi-3.c b/gcc/testsuite/gcc.target/arc/extvsi-3.c
new file mode 100644 (file)
index 0000000..2a466f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/extvsi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicts with -mcpu options" { *-*-* } { "-mcpu=*" } { "-mcpu=em" } } */
+/* { dg-options "-O2 -mcpu=em" } */
+struct S { int a : 5; };
+
+/* An extra parameter is added to ensure a different register is used for input and output. */
+int foo (int unused, struct S p)
+{
+  return p.a;
+}
+
+/* { dg-final { scan-assembler "and\\s+r0,r1,31" } } */
+/* { dg-final { scan-assembler "xor\\s+r0,r0,16" } } */
+/* { dg-final { scan-assembler "sub\\s+r0,r0,16" } } */