static bool loongarch_hard_regno_mode_ok_p[MAX_MACHINE_MODE]
[FIRST_PSEUDO_REGISTER];
-/* Index C is true if character C is a valid PRINT_OPERAND punctation
+/* Index C is true if character C is a valid PRINT_OPERAND punctuation
character. */
static bool loongarch_print_operand_punct[256];
local_cum = *get_cumulative_args (cum);
/* For a C23 variadic function w/o any named argument, and w/o an
- artifical argument for large return value, skip advancing args.
- There is such an artifical argument iff. arg.type is non-NULL
+ artificial argument for large return value, skip advancing args.
+ There is such an artificial argument iff. arg.type is non-NULL
(PR 114175). */
if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
|| arg.type != NULL_TREE)
/* Determine whether the upper 32 bits are sign-extended from the lower
32 bits. If it is, the instructions to load the high order can be
- ommitted. */
+ omitted. */
if (lu32i[sign31] && lu52i[sign31])
return cost;
/* If the lower 32 bits are the same as the upper 32 bits, just copy
/* Fill CODES with a sequence of rtl operations to load VALUE.
Return the number of operations needed.
- Split interger in loongarch_output_move. */
+ Split integer in loongarch_output_move. */
static unsigned int
loongarch_integer_cost (HOST_WIDE_INT value)
/* If we are performing LTO for a final link, and we have the
linker plugin so we know the resolution of the symbols, then
all GOT references are binding to external symbols or
- preemptable symbols. So the linker cannot relax them. */
+ preemptible symbols. So the linker cannot relax them. */
return (in_lto_p
&& !flag_incremental_link
&& HAVE_LTO_PLUGIN == 2
if (!loongarch_split_symbol_type (symbol_type))
return false;
- /* We can't tell size or alignment when we have BLKmode, so try extracing a
+ /* We can't tell size or alignment when we have BLKmode, so try extracting a
decl from the symbol if possible. */
if (mode == BLKmode)
{
}
/* Split one integer constant op[0] into two (op[1] and op[2]) for constant
- plus operation in a specific mode. The splitted constants can be added
+ plus operation in a specific mode. The split constants can be added
onto a register with a single instruction (addi.{d/w} or addu16i.d). */
void
return new_mem;
}
-/* Print the text for PRINT_OPERAND punctation character CH to FILE.
+/* Print the text for PRINT_OPERAND punctuation character CH to FILE.
The punctuation characters are:
'.' Print the name of the register with a hard-wired zero (zero or $r0).
/* In LASX, some permutation insn does not have the behavior that gcc expects
when compiler wants to emit a vector permutation.
- 1. What GCC provides via vectorize_vec_perm_const ()'s paramater:
+ 1. What GCC provides via vectorize_vec_perm_const ()'s parameter:
When GCC wants to performs a vector permutation, it provides two op
- reigster, one target register, and a selector.
+ register, one target register, and a selector.
In const vector permutation case, GCC provides selector as a char array
that contains original value; in variable vector permutation
(performs via vec_perm<mode> insn template), it provides a vector register.
idx = d->perm[0];
/* We will use xvrepl128vei.* insn to achieve the result, but we need
to make the high/low 128bit has the same contents that contain the
- value that we need to broardcast, because xvrepl128vei does the
- broardcast job from every 128bit of source register to
+ value that we need to broadcast, because xvrepl128vei does the
+ broadcast job from every 128bit of source register to
corresponded part of target register! (A deep sigh.) */
if (idx < d->nelt / 2)
{
return loongarch_cpu_sched_reassociation_width (&la_target, opc, mode);
}
-/* Implement extract a scalar element from vecotr register */
+/* Implement extract a scalar element from vector register */
void
loongarch_expand_vector_extract (rtx target, rtx vec, int elt)
if (!unsigned_p)
{
- /* Extract sign extention for each element comparing each element
+ /* Extract sign extension for each element comparing each element
with immediate zero. */
tmp = gen_reg_rtx (imode);
emit_insn (cmpFunc (tmp, operands[1], CONST0_RTX (imode)));
gseq = bb_seq (*empty_bb);
/* Function version dispatch is via IFUNC. IFUNC resolvers fire before
- constructors, so explicity call __init_loongarch_feature_bits here. */
+ constructors, so explicitly call __init_loongarch_feature_bits here. */
tree init_fn_type = build_function_type_list (void_type_node,
void_type_node,
NULL);
/* Output assembly to materialize the address of the stack canary value
into reg. The third argument, tmp, should be and should only be
non-NULL if the extreme code model is effective for the canary. If
- the fourth arugment, load, is true, the canary value is loaded into
+ the fourth argument, load, is true, the canary value is loaded into
the register.
- The assembly cannot be splitted due to security reason. */
+ The assembly cannot be split due to security reason. */
void
loongarch_output_asm_load_canary (rtx reg, rtx canary, rtx tmp)
{
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