mediatek: filogic: SDG-8733A: reset the radio through pcie3

GPIO 9 is the reset input of the MT7995 radio module, active low.
The old description used it as a PERST line on pcie0 with active
high polarity, so the port reset toggled the module reset at the
wrong time and with the wrong polarity.

Describe it as wifi-reset-gpios on pcie3, the port wired to the
module reset. The PCIe controller then releases the module from
reset before link training, with a 100 ms delay.

Signed-off-by: Chad Monroe <chad@monroe.io>
Link: https://github.com/openwrt/openwrt/pull/24352
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>

diff --git a/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi b/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi
index ce25d2892fdd8496436803a9eecf95984395f45d..5ebe63e89fbe5bd31a309a1898bb8e7b28110d2f 100644 (file)
--- a/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi
+++ b/target/linux/mediatek/dts/mt7988-smartrg-wifi-pcie3.dtsi
@@ -4,12 +4,15 @@
  * Author: Chad Monroe <chad.monroe@smartrg.com>
  *
  * Second PCIe function of the MT7995/MT7996-233 radio modules. The
- * main function (and the radio0 node) lives on pcie0.
+ * main function (and the radio0 node) lives on pcie0; the module
+ * reset is wired to the pcie3 port.
  */
 
 &pcie3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie3_1_pins>;
+       wifi-reset-gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+       wifi-reset-msleep = <100>;
        status = "okay";
 };
 

diff --git a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts
index f850b427c8eccc24bb4bcdf1b05aa93009f44cd6..fbb98cdd7869a2690e6f9900e2b9b1c8622c5e9e 100644 (file)
--- a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts
+++ b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts
@@ -183,7 +183,6 @@
 &pcie0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie0_1_pins>;
-       reset-gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
 };
 
 &pio {