spi: fsl-qspi: introduce sfa_size devtype data

In fsl_qspi_default_setup(), four registers define the size of blocks of
data to written to each of four chips that comprise SPI NOR flash storage.
They are currently defined to be the same as the AHB buffer size.

The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these
four sizes to be multiples of 1024 bytes.

Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if
non-zero, will be used instead of the AHB buffer size to define the size of
these chip regions.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20251027133008.360237-7-elder@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index 2c030dd6facc7e3cfcd202ac00f6db15fe80b3d5..46a3187b3354825ec89b56280f4c7283d6b9d1f6 100644 (file)
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data {
        unsigned int txfifo;
        int invalid_mstrid;
        unsigned int ahb_buf_size;
+       unsigned int sfa_size;
        unsigned int quirks;
        bool little_endian;
 };
@@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
 {
        void __iomem *base = q->iobase;
        u32 reg, addr_offset = 0;
+       u32 sfa_size;
        int ret;
 
        /* disable and unprepare clock to avoid glitch pass to controller */
@@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
         * In HW there can be a maximum of four chips on two buses with
         * two chip selects on each bus. We use four chip selects in SW
         * to differentiate between the four chips.
-        * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
-        * SFB2AD accordingly.
+        *
+        * By default we write the AHB buffer size to each chip, but
+        * a different size can be specified with devtype_data->sfa_size.
+        * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the
+        * top (end) of these four regions.
         */
-       qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
-                   base + QUADSPI_SFA1AD);
-       qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
-                   base + QUADSPI_SFA2AD);
-       qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
-                   base + QUADSPI_SFB1AD);
-       qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
-                   base + QUADSPI_SFB2AD);
+       sfa_size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size;
+       qspi_writel(q, addr_offset + 1 * sfa_size, base + QUADSPI_SFA1AD);
+       qspi_writel(q, addr_offset + 2 * sfa_size, base + QUADSPI_SFA2AD);
+       qspi_writel(q, addr_offset + 3 * sfa_size, base + QUADSPI_SFB1AD);
+       qspi_writel(q, addr_offset + 4 * sfa_size, base + QUADSPI_SFB2AD);
 
        q->selected = -1;