]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
wifi: ath12k: fix GCC_GCC_PCIE_HOT_RST definition for WCN7850
authorBaochen Qiang <quic_bqiang@quicinc.com>
Fri, 23 May 2025 02:23:05 +0000 (10:23 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 19 Jun 2025 13:32:27 +0000 (15:32 +0200)
[ Upstream commit 7588a893cde5385ad308400ff167d29a29913b3a ]

GCC_GCC_PCIE_HOT_RST is wrongly defined for WCN7850, causing kernel crash
on some specific platforms.

Since this register is divergent for WCN7850 and QCN9274, move it to
register table to allow different definitions. Then correct the register
address for WCN7850 to fix this issue.

Note IPQ5332 is not affected as it is not PCIe based device.

Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3

Signed-off-by: Baochen Qiang <quic_bqiang@quicinc.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Reported-by: Parth Pancholi <parth.pancholi@toradex.com>
Closes: https://lore.kernel.org/all/86899b2235a59c9134603beebe08f2bb0b244ea0.camel@gmail.com
Fixes: d889913205cf ("wifi: ath12k: driver for Qualcomm Wi-Fi 7 devices")
Tested-by: Parth Pancholi <parth.pancholi@toradex.com>
Link: https://patch.msgid.link/20250523-ath12k-wrong-global-reset-addr-v1-1-3b06eb556196@quicinc.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/wireless/ath/ath12k/hw.c
drivers/net/wireless/ath/ath12k/hw.h
drivers/net/wireless/ath/ath12k/pci.c
drivers/net/wireless/ath/ath12k/pci.h

index 5bffc428f19f598e8000edd08e6ba6f531344d18..e3eb22bb9e1cb9e0278ed9e88a6c1db7fcc141dc 100644 (file)
@@ -686,6 +686,8 @@ static const struct ath12k_hw_regs qcn9274_v1_regs = {
        .hal_umac_ce0_dest_reg_base = 0x01b81000,
        .hal_umac_ce1_src_reg_base = 0x01b82000,
        .hal_umac_ce1_dest_reg_base = 0x01b83000,
+
+       .gcc_gcc_pcie_hot_rst = 0x1e38338,
 };
 
 static const struct ath12k_hw_regs qcn9274_v2_regs = {
@@ -775,6 +777,8 @@ static const struct ath12k_hw_regs qcn9274_v2_regs = {
        .hal_umac_ce0_dest_reg_base = 0x01b81000,
        .hal_umac_ce1_src_reg_base = 0x01b82000,
        .hal_umac_ce1_dest_reg_base = 0x01b83000,
+
+       .gcc_gcc_pcie_hot_rst = 0x1e38338,
 };
 
 static const struct ath12k_hw_regs wcn7850_regs = {
@@ -860,6 +864,8 @@ static const struct ath12k_hw_regs wcn7850_regs = {
        .hal_umac_ce0_dest_reg_base = 0x01b81000,
        .hal_umac_ce1_src_reg_base = 0x01b82000,
        .hal_umac_ce1_dest_reg_base = 0x01b83000,
+
+       .gcc_gcc_pcie_hot_rst = 0x1e40304,
 };
 
 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = {
index acb81b5798ac175f0e2ab8938e13a7a31bbb3596..862b11325a9021448eced93d295275b8373591dd 100644 (file)
@@ -355,6 +355,8 @@ struct ath12k_hw_regs {
        u32 hal_reo_cmd_ring_base;
 
        u32 hal_reo_status_ring_base;
+
+       u32 gcc_gcc_pcie_hot_rst;
 };
 
 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type)
index 1068cc07bc9f6502a5f0de835938079c9212036b..26f4b440c26d27d3cb0cb6cf076580290c20b227 100644 (file)
@@ -290,10 +290,10 @@ static void ath12k_pci_enable_ltssm(struct ath12k_base *ab)
 
        ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val);
 
-       val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
+       val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab));
        val |= GCC_GCC_PCIE_HOT_RST_VAL;
-       ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
-       val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
+       ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST(ab), val);
+       val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab));
 
        ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
 
index 31584a7ad80eb9f55423905039050eac247aa1d8..9321674eef8b8f8b118f68900373c8b24705387f 100644 (file)
@@ -28,7 +28,9 @@
 #define PCIE_PCIE_PARF_LTSSM                   0x1e081b0
 #define PARM_LTSSM_VALUE                       0x111
 
-#define GCC_GCC_PCIE_HOT_RST                   0x1e38338
+#define GCC_GCC_PCIE_HOT_RST(ab) \
+       ((ab)->hw_params->regs->gcc_gcc_pcie_hot_rst)
+
 #define GCC_GCC_PCIE_HOT_RST_VAL               0x10
 
 #define PCIE_PCIE_INT_ALL_CLEAR                        0x1e08228