arm64: dts: qcom: sm8650: add iris DT node

Add DT entries for the sm8650 iris decoder.

Since the firmware is required to be signed, only enable
on Qualcomm development boards where the firmware is
available.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250613-topic-sm8x50-upstream-iris-8650-dt-v4-1-35ea7952f2d2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index d0912735b54e5090f9f213c2c9341e03effbbbff..259649d7dcd768ecf93c9473adc1738e7d715b6c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -894,6 +894,10 @@
        status = "okay";
 };
 
+&iris {
+       status = "okay";
+};
+
 &gpu {
        status = "okay";
 

diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 76ef43c10f77d8329ccf0a05c9d590a46372315f..8a957adbfb383411153506e46d4c9acfb02e3114 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -585,6 +585,10 @@
        };
 };
 
+&iris {
+       status = "okay";
+};
+
 &lpass_tlmm {
        spkr_1_sd_n_active: spkr-1-sd-n-active-state {
                pins = "gpio21";

diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index 71033fba21b56bc63620dca3e453c14191739675..7552d5d3fb4020e61d47242b447c9ecbec5f8d55 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -824,6 +824,10 @@
        status = "okay";
 };
 
+&iris {
+       status = "okay";
+};
+
 &gpu {
        status = "okay";
 

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 076682747699083cb7401383f24d5264f7cbec51..e14d3d778b71bbbd0c8fcc851eebc9df9ac09c31 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4962,6 +4962,99 @@
                        };
                };
 
+               iris: video-codec@aa00000 {
+                       compatible = "qcom,sm8650-iris";
+                       reg = <0 0x0aa00000 0 0xf0000>;
+
+                       interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
+
+                       power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+                                       <&videocc VIDEO_CC_MVS0_GDSC>,
+                                       <&rpmhpd RPMHPD_MXC>,
+                                       <&rpmhpd RPMHPD_MMCX>;
+                       power-domain-names = "venus",
+                                            "vcodec0",
+                                            "mxc",
+                                            "mmcx";
+
+                       operating-points-v2 = <&iris_opp_table>;
+
+                       clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+                                <&videocc VIDEO_CC_MVS0C_CLK>,
+                                <&videocc VIDEO_CC_MVS0_CLK>;
+                       clock-names = "iface",
+                                     "core",
+                                     "vcodec0_core";
+
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "cpu-cfg",
+                                            "video-mem";
+
+                       memory-region = <&video_mem>;
+
+                       resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+                                <&videocc VIDEO_CC_XO_CLK_ARES>,
+                                <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+                       reset-names = "bus",
+                                     "xo",
+                                     "core";
+
+                       iommus = <&apps_smmu 0x1940 0>,
+                                <&apps_smmu 0x1947 0>;
+
+                       dma-coherent;
+
+                       /*
+                        * IRIS firmware is signed by vendors, only
+                        * enable in boards where the proper signed firmware
+                        * is available.
+                        */
+                       status = "disabled";
+
+                       iris_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-196000000 {
+                                       opp-hz = /bits/ 64 <196000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs_d1>,
+                                                       <&rpmhpd_opp_low_svs_d1>;
+                               };
+
+                               opp-300000000 {
+                                       opp-hz = /bits/ 64 <300000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>,
+                                                       <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-380000000 {
+                                       opp-hz = /bits/ 64 <380000000>;
+                                       required-opps = <&rpmhpd_opp_svs>,
+                                                       <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-435000000 {
+                                       opp-hz = /bits/ 64 <435000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>,
+                                                       <&rpmhpd_opp_svs_l1>;
+                               };
+
+                               opp-480000000 {
+                                       opp-hz = /bits/ 64 <480000000>;
+                                       required-opps = <&rpmhpd_opp_nom>,
+                                                       <&rpmhpd_opp_nom>;
+                               };
+
+                               opp-533333334 {
+                                       opp-hz = /bits/ 64 <533333334>;
+                                       required-opps = <&rpmhpd_opp_turbo>,
+                                                       <&rpmhpd_opp_turbo>;
+                               };
+                       };
+               };
+
                videocc: clock-controller@aaf0000 {
                        compatible = "qcom,sm8650-videocc";
                        reg = <0 0x0aaf0000 0 0x10000>;