display->irq.vlv_imr_mask = ~0u;
}
-void vlv_display_irq_reset(struct intel_display *display)
+static void vlv_display_irq_reset(struct intel_display *display)
{
spin_lock_irq(&display->irq.lock);
if (display->irq.vlv_display_irqs_enabled)
spin_unlock_irq(&display->irq.lock);
}
-void i9xx_display_irq_reset(struct intel_display *display)
+static void i9xx_display_irq_reset(struct intel_display *display)
{
if (HAS_HOTPLUG(display)) {
i915_hotplug_interrupt_update(display, 0xffffffff, 0);
intel_de_write(display, SERR_INT, 0xffffffff);
}
-void ilk_display_irq_reset(struct intel_display *display)
+static void ilk_display_irq_reset(struct intel_display *display)
{
irq_reset(display, DE_IRQ_REGS);
display->irq.ilk_de_imr_mask = ~0u;
ibx_display_irq_reset(display);
}
-void gen8_display_irq_reset(struct intel_display *display)
+static void gen8_display_irq_reset(struct intel_display *display)
{
enum pipe pipe;
- if (!HAS_DISPLAY(display))
- return;
-
intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
ibx_display_irq_reset(display);
}
-void gen11_display_irq_reset(struct intel_display *display)
+static void gen11_display_irq_reset(struct intel_display *display)
{
enum pipe pipe;
u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
- if (!HAS_DISPLAY(display))
- return;
-
intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
if (DISPLAY_VER(display) >= 12) {
void (*reset)(struct intel_display *display);
};
+static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
+ .reset = gen11_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
+ .reset = gen8_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
+ .reset = vlv_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
+ .reset = ilk_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs i965_display_irq_funcs = {
+ .reset = i9xx_display_irq_reset,
+};
+
+static const struct intel_display_irq_funcs i915_display_irq_funcs = {
+ .reset = i9xx_display_irq_reset,
+};
+
+void intel_display_irq_reset(struct intel_display *display)
+{
+ if (!HAS_DISPLAY(display))
+ return;
+
+ display->irq.funcs->reset(display);
+}
+
void intel_display_irq_init(struct intel_display *display)
{
spin_lock_init(&display->irq.lock);
INIT_WORK(&display->irq.vblank_notify_work,
intel_display_vblank_notify_work);
+
+ if (DISPLAY_VER(display) >= 11)
+ display->irq.funcs = &gen11_display_irq_funcs;
+ else if (display->platform.cherryview || display->platform.valleyview)
+ display->irq.funcs = &vlv_display_irq_funcs;
+ else if (DISPLAY_VER(display) >= 8)
+ display->irq.funcs = &gen8_display_irq_funcs;
+ else if (DISPLAY_VER(display) >= 5)
+ display->irq.funcs = &ilk_display_irq_funcs;
+ else if (DISPLAY_VER(display) == 4)
+ display->irq.funcs = &i965_display_irq_funcs;
+ else
+ display->irq.funcs = &i915_display_irq_funcs;
}
struct intel_display_irq_snapshot {
struct intel_display *display = dev_priv->display;
/* The master interrupt enable is in DEIER, reset display irq first */
- ilk_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen5_gt_irq_reset(to_gt(dev_priv));
}
gen5_gt_irq_reset(to_gt(dev_priv));
- vlv_display_irq_reset(display);
+ intel_display_irq_reset(display);
}
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
gen8_master_intr_disable(intel_uncore_regs(uncore));
gen8_gt_irq_reset(to_gt(dev_priv));
- gen8_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
}
gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
for_each_gt(gt, dev_priv, i)
gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
- vlv_display_irq_reset(display);
+ intel_display_irq_reset(display);
}
static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
struct intel_display *display = dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
- i9xx_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
struct intel_display *display = dev_priv->display;
struct intel_uncore *uncore = &dev_priv->uncore;
- i9xx_display_irq_reset(display);
+ intel_display_irq_reset(display);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);