]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
realtek: add dts helper for internal phy with serdes
authorMarkus Stockhausen <markus.stockhausen@gmx.de>
Tue, 20 May 2025 07:37:10 +0000 (03:37 -0400)
committerRobert Marko <robimarko@gmail.com>
Sun, 22 Jun 2025 14:37:32 +0000 (16:37 +0200)
Until now only the RTL930x devices make use of the following notation.

  phy8: ethernet-phy@8 {
    compatible = "ethernet-phy-ieee802.3-c22";
    phy-is-integrated;
    reg = <8>;
    sds = <3>;
  };

This indicates that the link is driven by a serdes directly without
external phy. As the devices have multiple serdes it must be clarified
what serdes is responsible for that port.

Nevertheless all other devices have the same requirements. E.g. RTL838x
usually drives port 24 from serdes 4 and port 26 from serdes 5. All this
currently works because the driver has a lot of hardcoded port/serdes
mapping.

Make the situation better by adding dts helpers that can describe the
topology as needed.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
target/linux/realtek/dts/rtl838x.dtsi
target/linux/realtek/dts/rtl839x.dtsi
target/linux/realtek/dts/rtl930x.dtsi
target/linux/realtek/dts/rtl931x.dtsi

index 8f44de8bdcfd9bf8d20da58dd4ec9a9924b68203..035ff029c9a8863fa12ff95980227953bea10663 100644 (file)
                phy-is-integrated; \
        };
 
+#define INTERNAL_PHY_SDS(n, s) \
+       phy##n: ethernet-phy@##n { \
+               reg = <##n>; \
+               compatible = "ethernet-phy-ieee802.3-c22"; \
+               phy-is-integrated; \
+               sds = <##s>; \
+       };
+
 #define EXTERNAL_PHY(n) \
        phy##n: ethernet-phy@##n { \
                reg = <##n>; \
index 98c69a5d34ba400f6bf91f92b5a5a52030d1b86c..29458269faf190687a53f9c2156f890305dce88c 100644 (file)
                phy-is-integrated; \
        };
 
+#define INTERNAL_PHY_SDS(n, s) \
+       phy##n: ethernet-phy@##n { \
+               reg = <##n>; \
+               compatible = "ethernet-phy-ieee802.3-c22"; \
+               phy-is-integrated; \
+               sds = <##s>; \
+       };
+
 #define EXTERNAL_PHY(n) \
        phy##n: ethernet-phy@##n { \
                reg = <##n>; \
index 34d1ede54c9e6c19c1b4c72388c6935f123af7c9..947f0d9be5f1991ad1dc1a186bc386f7126fa3d3 100644 (file)
@@ -2,6 +2,14 @@
 
 /dts-v1/;
 
+#define INTERNAL_PHY_SDS(n, s) \
+       phy##n: ethernet-phy@##n { \
+               reg = <##n>; \
+               compatible = "ethernet-phy-ieee802.3-c22"; \
+               phy-is-integrated; \
+               sds = <##s>; \
+       };
+
 / {
        #address-cells = <1>;
        #size-cells = <1>;
index 7ecfd2a0c6e2d5ffbb181717b7bbd34dc30ff07c..c7feef4724ae769270ff5ef69240962fb7e7cb5f 100644 (file)
@@ -2,6 +2,16 @@
 
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 
+/dts-v1/;
+
+#define INTERNAL_PHY_SDS(n, s) \
+       phy##n: ethernet-phy@##n { \
+               reg = <##n>; \
+               compatible = "ethernet-phy-ieee802.3-c22"; \
+               phy-is-integrated; \
+               sds = <##s>; \
+       };
+
 / {
        #address-cells = <1>;
        #size-cells = <1>;