arm64: dts: imx952-evk: Change the usdhc1_200mhz drive strength to DSE4

Set usdhc1_200mhz drive strength need to use DSE4, according to validation
team's suggestion,

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts
index 2c753fcbae3c5d545f5d835bd70492667061d626..e5d989bd7c7b7f8b7c0b0afd0ae8f108110e4a49 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx952-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts
@@ -159,17 +159,17 @@
 
        pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
-                       IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK            0x15fe
-                       IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD            0x13fe
-                       IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0        0x13fe
-                       IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1        0x13fe
-                       IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2        0x13fe
-                       IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3        0x13fe
-                       IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4        0x13fe
-                       IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5        0x13fe
-                       IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6        0x13fe
-                       IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7        0x13fe
-                       IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE      0x15fe
+                       IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK            0x159e
+                       IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD            0x139e
+                       IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0        0x139e
+                       IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1        0x139e
+                       IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2        0x139e
+                       IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3        0x139e
+                       IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4        0x139e
+                       IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5        0x139e
+                       IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6        0x139e
+                       IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7        0x139e
+                       IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE      0x159e
                >;
        };