#define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 16)
#define TI_CSI2RX_MAX_PIX_PER_CLK 4
-#define TI_CSI2RX_NUM_CTX 1
+#define TI_CSI2RX_MAX_CTX 32
/*
* There are no hard limits on the width or height. The DMA engine can handle
#define TI_CSI2RX_PAD_SINK 0
#define TI_CSI2RX_PAD_FIRST_SOURCE 1
-#define TI_CSI2RX_NUM_SOURCE_PADS 1
-#define TI_CSI2RX_NUM_PADS (1 + TI_CSI2RX_NUM_SOURCE_PADS)
+#define TI_CSI2RX_MAX_SOURCE_PADS TI_CSI2RX_MAX_CTX
+#define TI_CSI2RX_MAX_PADS (1 + TI_CSI2RX_MAX_SOURCE_PADS)
#define DRAIN_TIMEOUT_MS 50
#define DRAIN_BUFFER_SIZE SZ_32K
struct device *dev;
void __iomem *shim;
unsigned int enable_count;
+ unsigned int num_ctx;
struct v4l2_device v4l2_dev;
struct media_device mdev;
struct media_pipeline pipe;
- struct media_pad pads[TI_CSI2RX_NUM_PADS];
+ struct media_pad pads[TI_CSI2RX_MAX_PADS];
struct v4l2_async_notifier notifier;
struct v4l2_subdev *source;
struct v4l2_subdev subdev;
- struct ti_csi2rx_ctx ctx[TI_CSI2RX_NUM_CTX];
+ struct ti_csi2rx_ctx ctx[TI_CSI2RX_MAX_CTX];
u8 pix_per_clk;
/* Buffer to drain stale data from PSI-L endpoint */
struct {
return ret;
/* Create and link video nodes for all DMA contexts */
- for (i = 0; i < TI_CSI2RX_NUM_CTX; i++) {
+ for (i = 0; i < csi->num_ctx; i++) {
struct ti_csi2rx_ctx *ctx = &csi->ctx[i];
struct video_device *vdev = &ctx->vdev;
csi->pads[TI_CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
for (unsigned int i = TI_CSI2RX_PAD_FIRST_SOURCE;
- i < TI_CSI2RX_NUM_PADS; i++)
+ i < TI_CSI2RX_PAD_FIRST_SOURCE + csi->num_ctx; i++)
csi->pads[i].flags = MEDIA_PAD_FL_SOURCE;
- ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(csi->pads),
+ ret = media_entity_pads_init(&sd->entity,
+ TI_CSI2RX_PAD_FIRST_SOURCE + csi->num_ctx,
csi->pads);
if (ret)
goto unregister_media;
static int ti_csi2rx_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
struct ti_csi2rx_dev *csi;
- int ret, i;
+ int ret = 0, i, count;
csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
if (!csi)
if (!csi->drain.vaddr)
return -ENOMEM;
+ /* Only use as many contexts as the number of DMA channels allocated. */
+ count = of_property_count_strings(np, "dma-names");
+ if (count < 0) {
+ dev_err(csi->dev, "Failed to get DMA channel count: %d\n", count);
+ ret = count;
+ goto err_dma_chan;
+ }
+
+ csi->num_ctx = count;
+ if (csi->num_ctx > TI_CSI2RX_MAX_CTX) {
+ dev_err(csi->dev,
+ "%u DMA channels passed. Maximum is %u.\n",
+ csi->num_ctx, TI_CSI2RX_MAX_CTX);
+ ret = -EINVAL;
+ goto err_dma_chan;
+ }
+
ret = ti_csi2rx_v4l2_init(csi);
if (ret)
- goto err_v4l2;
+ goto err_dma_chan;
- for (i = 0; i < TI_CSI2RX_NUM_CTX; i++) {
+ for (i = 0; i < csi->num_ctx; i++) {
csi->ctx[i].idx = i;
csi->ctx[i].csi = csi;
ret = ti_csi2rx_init_ctx(&csi->ctx[i]);
for (; i >= 0; i--)
ti_csi2rx_cleanup_ctx(&csi->ctx[i]);
ti_csi2rx_cleanup_v4l2(csi);
-err_v4l2:
+err_dma_chan:
dma_free_coherent(csi->dev, csi->drain.len, csi->drain.vaddr,
csi->drain.paddr);
return ret;
struct ti_csi2rx_dev *csi = platform_get_drvdata(pdev);
unsigned int i;
- for (i = 0; i < TI_CSI2RX_NUM_CTX; i++)
+ for (i = 0; i < csi->num_ctx; i++)
ti_csi2rx_cleanup_ctx(&csi->ctx[i]);
ti_csi2rx_cleanup_notifier(csi);