&ipq5424_apss_pll,
};
-static struct qcom_cc_driver_data ipa5424_apss_driver_data = {
+static const struct qcom_cc_driver_data ipa5424_apss_driver_data = {
.alpha_plls = ipa5424_apss_plls,
.num_alpha_plls = ARRAY_SIZE(ipa5424_apss_plls),
};
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
+static const struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
.alpha_plls = cam_bist_mclk_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls),
.clk_cbcrs = cam_bist_mclk_cc_kaanapali_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
+static const struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
.alpha_plls = cam_bist_mclk_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_plls),
.clk_cbcrs = cam_bist_mclk_cc_sm8750_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_kaanapali_driver_data = {
.alpha_plls = cam_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_kaanapali_plls),
.clk_cbcrs = cam_cc_kaanapali_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_milos_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_milos_driver_data = {
.alpha_plls = cam_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_milos_plls),
.clk_cbcrs = cam_cc_milos_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_qcs615_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_qcs615_driver_data = {
.alpha_plls = cam_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_qcs615_plls),
};
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_sc8180x_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_sc8180x_driver_data = {
.alpha_plls = cam_cc_sc8180x_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sc8180x_plls),
.clk_cbcrs = cam_cc_sc8180x_critical_cbcrs,
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
-static struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
.alpha_plls = cam_cc_sm8450_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8450_plls),
.clk_cbcrs = cam_cc_sm8450_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
.alpha_plls = cam_cc_sm8550_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8550_plls),
.clk_cbcrs = cam_cc_sm8550_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_sm8650_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_sm8650_driver_data = {
.alpha_plls = cam_cc_sm8650_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8650_plls),
.clk_cbcrs = cam_cc_sm8650_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_sm8750_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_sm8750_driver_data = {
.alpha_plls = cam_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8750_plls),
.clk_cbcrs = cam_cc_sm8750_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = {
+static const struct qcom_cc_driver_data cam_cc_x1e80100_driver_data = {
.alpha_plls = cam_cc_x1e80100_plls,
.num_alpha_plls = ARRAY_SIZE(cam_cc_x1e80100_plls),
.clk_cbcrs = cam_cc_x1e80100_critical_cbcrs,
size_t num_icc_hws;
unsigned int icc_first_node_id;
bool use_rpm;
- struct qcom_cc_driver_data *driver_data;
+ const struct qcom_cc_driver_data *driver_data;
};
/**
regmap_set_bits(regmap, DISP_CC_MISC_CMD, BIT(4));
}
-static struct qcom_cc_driver_data disp_cc_eliza_driver_data = {
+static const struct qcom_cc_driver_data disp_cc_eliza_driver_data = {
.alpha_plls = disp_cc_eliza_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_eliza_plls),
.clk_cbcrs = disp_cc_eliza_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data disp_cc_glymur_driver_data = {
+static const struct qcom_cc_driver_data disp_cc_glymur_driver_data = {
.alpha_plls = disp_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_glymur_plls),
.clk_cbcrs = disp_cc_glymur_critical_cbcrs,
regmap_update_bits(regmap, DISP_CC_MISC_CMD, BIT(4), BIT(4));
}
-static struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = {
+static const struct qcom_cc_driver_data disp_cc_kaanapali_driver_data = {
.alpha_plls = disp_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_kaanapali_plls),
.clk_cbcrs = disp_cc_kaanapali_critical_cbcrs,
}
-static struct qcom_cc_driver_data disp_cc_milos_driver_data = {
+static const struct qcom_cc_driver_data disp_cc_milos_driver_data = {
.alpha_plls = disp_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_milos_plls),
.clk_cbcrs = disp_cc_milos_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data disp_cc_qcs615_driver_data = {
+static const struct qcom_cc_driver_data disp_cc_qcs615_driver_data = {
.alpha_plls = disp_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(disp_cc_qcs615_plls),
.clk_cbcrs = disp_cc_qcs615_critical_cbcrs,
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
}
-static struct qcom_cc_driver_data gcc_eliza_driver_data = {
+static const struct qcom_cc_driver_data gcc_eliza_driver_data = {
.clk_cbcrs = gcc_eliza_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_eliza_critical_cbcrs),
.dfs_rcgs = gcc_eliza_dfs_clocks,
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
}
-static struct qcom_cc_driver_data gcc_glymur_driver_data = {
+static const struct qcom_cc_driver_data gcc_glymur_driver_data = {
.clk_cbcrs = gcc_glymur_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_glymur_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
}
-static struct qcom_cc_driver_data gcc_kaanapali_driver_data = {
+static const struct qcom_cc_driver_data gcc_kaanapali_driver_data = {
.clk_cbcrs = gcc_kaanapali_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_kaanapali_critical_cbcrs),
.dfs_rcgs = gcc_dfs_clocks,
.fast_io = true,
};
-static struct qcom_cc_driver_data gcc_milos_driver_data = {
+static const struct qcom_cc_driver_data gcc_milos_driver_data = {
.clk_cbcrs = gcc_milos_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_milos_critical_cbcrs),
.dfs_rcgs = gcc_milos_dfs_clocks,
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
}
-static struct qcom_cc_driver_data gcc_sc8180x_driver_data = {
+static const struct qcom_cc_driver_data gcc_sc8180x_driver_data = {
.clk_cbcrs = gcc_sc8180x_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_sc8180x_critical_cbcrs),
.dfs_rcgs = gcc_sc8180x_dfs_clocks,
.fast_io = true,
};
-static struct qcom_cc_driver_data gpu_cc_glymur_driver_data = {
+static const struct qcom_cc_driver_data gpu_cc_glymur_driver_data = {
.alpha_plls = gpu_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_glymur_plls),
.clk_cbcrs = gpu_cc_glymur_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data = {
+static const struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data = {
.alpha_plls = gpu_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_kaanapali_plls),
.clk_cbcrs = gpu_cc_kaanapali_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data gpu_cc_milos_driver_data = {
+static const struct qcom_cc_driver_data gpu_cc_milos_driver_data = {
.alpha_plls = gpu_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_milos_plls),
.clk_cbcrs = gpu_cc_milos_critical_cbcrs,
regmap_update_bits(regmap, 0x1024, 0x00800000, 0x00800000);
}
-static struct qcom_cc_driver_data gpu_cc_qcs615_driver_data = {
+static const struct qcom_cc_driver_data gpu_cc_qcs615_driver_data = {
.alpha_plls = gpu_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_qcs615_plls),
.clk_cbcrs = gpu_cc_qcs615_critical_cbcrs,
regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0));
}
-static struct qcom_cc_driver_data video_cc_glymur_driver_data = {
+static const struct qcom_cc_driver_data video_cc_glymur_driver_data = {
.alpha_plls = video_cc_glymur_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_glymur_plls),
.clk_cbcrs = video_cc_glymur_critical_cbcrs,
regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK);
}
-static struct qcom_cc_driver_data video_cc_kaanapali_driver_data = {
+static const struct qcom_cc_driver_data video_cc_kaanapali_driver_data = {
.alpha_plls = video_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_kaanapali_plls),
.clk_cbcrs = video_cc_kaanapali_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data video_cc_milos_driver_data = {
+static const struct qcom_cc_driver_data video_cc_milos_driver_data = {
.alpha_plls = video_cc_milos_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_milos_plls),
.clk_cbcrs = video_cc_milos_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data video_cc_qcs615_driver_data = {
+static const struct qcom_cc_driver_data video_cc_qcs615_driver_data = {
.alpha_plls = video_cc_qcs615_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_qcs615_plls),
.clk_cbcrs = video_cc_qcs615_critical_cbcrs,
.fast_io = true,
};
-static struct qcom_cc_driver_data video_cc_sm8450_driver_data = {
+static const struct qcom_cc_driver_data video_cc_sm8450_driver_data = {
.alpha_plls = video_cc_sm8450_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_sm8450_plls),
.clk_cbcrs = video_cc_sm8450_critical_cbcrs,
regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0));
}
-static struct qcom_cc_driver_data video_cc_sm8750_driver_data = {
+static const struct qcom_cc_driver_data video_cc_sm8750_driver_data = {
.alpha_plls = video_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_sm8750_plls),
.clk_cbcrs = video_cc_sm8750_critical_cbcrs,