drm/i915: s/min_cdck[]/plane_min_cdclk[]/

Rename crtc_state->min_cdclk[] into crtc_state->plane_min_cdclk[]
to better reflect what it represents.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251013201236.30084-7-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 8fb19e605832b06d4062ffadaf991259eb2048d2..6c477b6a7b8ac816fde2ae41718ab86bca67948d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2828,7 +2828,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
        int min_cdclk = 0;
 
        for_each_intel_plane_on_crtc(display->drm, crtc, plane)
-               min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
+               min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]);
 
        return min_cdclk;
 }

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 87b7cec35320f8490e4634d83b146804742a8121..f77d120733fd1779b41994bffa4472eb9755f461 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1192,7 +1192,7 @@ struct intel_crtc_state {
 
        struct intel_crtc_wm_state wm;
 
-       int min_cdclk[I915_MAX_PLANES];
+       int plane_min_cdclk[I915_MAX_PLANES];
 
        /* for packed/planar CbCr */
        u32 data_rate[I915_MAX_PLANES];

diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index deb877b2aebda45176dc05854b0e50c9fcaea775..d5c432b613cef417e8cd19e633b2c6ca10163540 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -853,16 +853,16 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
                         */
                        if (plane_state->uapi.visible && plane->min_cdclk) {
                                if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)
-                                       crtc_state->min_cdclk[plane->id] =
+                                       crtc_state->plane_min_cdclk[plane->id] =
                                                DIV_ROUND_UP(crtc_state->pixel_rate, 2);
                                else
-                                       crtc_state->min_cdclk[plane->id] =
+                                       crtc_state->plane_min_cdclk[plane->id] =
                                                crtc_state->pixel_rate;
                        }
                        drm_dbg_kms(display->drm,
                                    "[PLANE:%d:%s] min_cdclk %d kHz\n",
                                    plane->base.base.id, plane->base.name,
-                                   crtc_state->min_cdclk[plane->id]);
+                                   crtc_state->plane_min_cdclk[plane->id]);
                }
 
                intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,

diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 074de9275951fdfb29dbb991dad910f925b0ac3d..78329deb395adaf7825e22f2a562b12b4c7080c3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -304,7 +304,7 @@ static void intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 
        new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 
-       new_crtc_state->min_cdclk[plane->id] =
+       new_crtc_state->plane_min_cdclk[plane->id] =
                plane->min_cdclk(new_crtc_state, plane_state);
 }
 
@@ -391,7 +391,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
        crtc_state->data_rate_y[plane->id] = 0;
        crtc_state->rel_data_rate[plane->id] = 0;
        crtc_state->rel_data_rate_y[plane->id] = 0;
-       crtc_state->min_cdclk[plane->id] = 0;
+       crtc_state->plane_min_cdclk[plane->id] = 0;
 
        plane_state->uapi.visible = false;
 }