return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll);
}
+static int mtl_pll_get_freq(struct intel_display *display,
+ const struct intel_dpll *pll,
+ const struct intel_dpll_hw_state *dpll_hw_state)
+{
+ struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+ if (drm_WARN_ON(display->drm, !encoder))
+ return -EINVAL;
+
+ return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll);
+}
+
static const struct intel_dpll_funcs mtl_pll_funcs = {
.get_hw_state = mtl_pll_get_hw_state,
+ .get_freq = mtl_pll_get_freq,
};
static const struct dpll_info mtl_plls[] = {