Make `--cache-sim=no` the default for Cachegrind.

Also, don't print cache simulation details in the `desc:` line when the
cache simulation is disabled.

Docs changes are yet to come.

diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 927f3fb328cdec7342f8d69fb79daa29cf0bb3ce..c4e111aa30671540fa08ec916f9bf650402b9542 100644 (file)
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -57,7 +57,7 @@
 /*--- Options                                              ---*/
 /*------------------------------------------------------------*/
 
-static Bool  clo_cache_sim  = True;  /* do cache simulation? */
+static Bool  clo_cache_sim  = False; /* do cache simulation? */
 static Bool  clo_branch_sim = False; /* do branch simulation? */
 static const HChar* clo_cachegrind_out_file = "cachegrind.out.%p";
 
@@ -1391,21 +1391,23 @@ static void fprint_CC_table_and_calc_totals(void)
    if (fp == NULL) {
       // If the file can't be opened for whatever reason (conflict
       // between multiple cachegrinded processes?), give up now.
-      VG_(umsg)("error: can't open cache simulation output file '%s'\n",
+      VG_(umsg)("error: can't open output data file '%s'\n",
                 cachegrind_out_file );
-      VG_(umsg)("       ... so simulation results will be missing.\n");
+      VG_(umsg)("       ... so detailed results will be missing.\n");
       VG_(free)(cachegrind_out_file);
       return;
    } else {
       VG_(free)(cachegrind_out_file);
    }
 
-   // "desc:" lines (giving I1/D1/LL cache configuration).  The spaces after
-   // the 2nd colon makes cg_annotate's output look nicer.
-   VG_(fprintf)(fp,  "desc: I1 cache:         %s\n"
-                     "desc: D1 cache:         %s\n"
-                     "desc: LL cache:         %s\n",
-                     I1.desc_line, D1.desc_line, LL.desc_line);
+   if (clo_cache_sim) {
+      // "desc:" lines (giving I1/D1/LL cache configuration). The spaces after
+      // the 2nd colon makes cg_annotate's output look nicer.
+      VG_(fprintf)(fp,  "desc: I1 cache:         %s\n"
+                        "desc: D1 cache:         %s\n"
+                        "desc: LL cache:         %s\n",
+                        I1.desc_line, D1.desc_line, LL.desc_line);
+   }
 
    // "cmd:" line
    VG_(fprintf)(fp, "cmd: %s", VG_(args_the_exename));

diff --git a/cachegrind/tests/ann-diff1.stderr.exp b/cachegrind/tests/ann-diff1.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/ann-diff1.stderr.exp
+++ b/cachegrind/tests/ann-diff1.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/ann-diff2.stderr.exp b/cachegrind/tests/ann-diff2.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/ann-diff2.stderr.exp
+++ b/cachegrind/tests/ann-diff2.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/ann-merge1.stderr.exp b/cachegrind/tests/ann-merge1.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/ann-merge1.stderr.exp
+++ b/cachegrind/tests/ann-merge1.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/ann1a.stderr.exp b/cachegrind/tests/ann1a.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/ann1a.stderr.exp
+++ b/cachegrind/tests/ann1a.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/ann1b.stderr.exp b/cachegrind/tests/ann1b.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/ann1b.stderr.exp
+++ b/cachegrind/tests/ann1b.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/ann2.stderr.exp b/cachegrind/tests/ann2.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/ann2.stderr.exp
+++ b/cachegrind/tests/ann2.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/chdir.stderr.exp b/cachegrind/tests/chdir.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/chdir.stderr.exp
+++ b/cachegrind/tests/chdir.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/dlclose.stderr.exp b/cachegrind/tests/dlclose.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/dlclose.stderr.exp
+++ b/cachegrind/tests/dlclose.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/notpower2.vgtest b/cachegrind/tests/notpower2.vgtest
index 21caffe94eecff9132d2caaf2b3942497efc67cd..bf05bb41c792252000260c39f26d8084fc40fbff 100644 (file)
--- a/cachegrind/tests/notpower2.vgtest
+++ b/cachegrind/tests/notpower2.vgtest
@@ -1,3 +1,3 @@
 prog: ../../tests/true
-vgopts: --I1=32768,8,64 --D1=24576,6,64 --LL=3145728,12,64
+vgopts: --cache-sim=yes --I1=32768,8,64 --D1=24576,6,64 --LL=3145728,12,64
 cleanup: rm cachegrind.out.*

diff --git a/cachegrind/tests/wrap5.stderr.exp b/cachegrind/tests/wrap5.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/wrap5.stderr.exp
+++ b/cachegrind/tests/wrap5.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate:

diff --git a/cachegrind/tests/x86/fpu-28-108.stderr.exp b/cachegrind/tests/x86/fpu-28-108.stderr.exp
index e8084c12c31786664f7954f1d874288066d86f0a..ec68407b27ce0f774afb5b00290642cd68aaf5b1 100644 (file)
--- a/cachegrind/tests/x86/fpu-28-108.stderr.exp
+++ b/cachegrind/tests/x86/fpu-28-108.stderr.exp
@@ -1,17 +1,3 @@
 
 
 I   refs:
-I1  misses:
-LLi misses:
-I1  miss rate:
-LLi miss rate:
-
-D   refs:
-D1  misses:
-LLd misses:
-D1  miss rate:
-LLd miss rate:
-
-LL refs:
-LL misses:
-LL miss rate: