#define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2)
#define SYS_REG_CS1_COL_MASK 3
+/* Get sdram type decode from reg */
+u8 rockchip_sdram_type(phys_addr_t reg);
+
/* Get sdram size decode from reg */
size_t rockchip_sdram_size(phys_addr_t reg);
return 0;
}
+u8 rockchip_sdram_type(phys_addr_t reg)
+{
+ u32 dram_type, version;
+ u32 sys_reg2 = readl(reg);
+ u32 sys_reg3 = readl(reg + 4);
+
+ dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
+ version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
+ if (version >= 3)
+ dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
+ SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
+
+ return dram_type;
+}
+
size_t rockchip_sdram_size(phys_addr_t reg)
{
u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;