}
static inline u64
-intel_de_read64_2x32(struct intel_display *display,
- i915_reg_t lower_reg, i915_reg_t upper_reg)
+intel_de_read64_2x32_volatile(struct intel_display *display,
+ i915_reg_t lower_reg, i915_reg_t upper_reg)
{
u64 val;
* we get a low value that's stable across two reads of the high
* register.
*/
- frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
- PIPEFRAME(display, pipe));
+ frame = intel_de_read64_2x32_volatile(display, PIPEFRAMEPIXEL(display, pipe),
+ PIPEFRAME(display, pipe));
pixel = frame & PIPE_PIXEL_MASK;
frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
if (crtc_state->cmrr.enable) {
crtc_state->cmrr.cmrr_n =
- intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
- TRANS_CMRR_N_HI(display, cpu_transcoder));
+ intel_de_read64_2x32_volatile(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
+ TRANS_CMRR_N_HI(display, cpu_transcoder));
crtc_state->cmrr.cmrr_m =
- intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
- TRANS_CMRR_M_HI(display, cpu_transcoder));
+ intel_de_read64_2x32_volatile(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
+ TRANS_CMRR_M_HI(display, cpu_transcoder));
}
if (DISPLAY_VER(display) >= 13) {