iio: pressure: mprls0025pa: fix SPI CS delay violation

Based on the sensor datasheet in chapter 7.6 SPI timing, Table 20,
during the SPI transfer there is a minimum time interval requirement
between the CS being asserted and the first clock edge (tHDSS).
This minimum interval of 2.5us is being violated if two consecutive SPI
transfers are queued up.

Fixes: a0858f0cd28e ("iio: pressure: mprls0025pa add SPI driver")
Datasheet: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/micropressure-mpr-series/documents/sps-siot-mpr-series-datasheet-32332628-ciid-172626.pdf?download=false
Signed-off-by: Petre Rodan <petre.rodan@subdimension.ro>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/pressure/mprls0025pa_spi.c b/drivers/iio/pressure/mprls0025pa_spi.c
index e6bb75de341191079dc3b8ae4299173c91cb7307..cf17eb2e720830930a3e275579ca5a3da8bb5c82 100644 (file)
--- a/drivers/iio/pressure/mprls0025pa_spi.c
+++ b/drivers/iio/pressure/mprls0025pa_spi.c
@@ -8,6 +8,7 @@
  *  https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/micropressure-mpr-series/documents/sps-siot-mpr-series-datasheet-32332628-ciid-172626.pdf
  */
 
+#include <linux/array_size.h>
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/mod_devicetable.h>
@@ -40,17 +41,25 @@ static int mpr_spi_xfer(struct mpr_data *data, const u8 cmd, const u8 pkt_len)
 {
        struct spi_device *spi = to_spi_device(data->dev);
        struct mpr_spi_buf *buf = spi_get_drvdata(spi);
-       struct spi_transfer xfer = { };
+       struct spi_transfer xfers[2] = { };
 
        if (pkt_len > MPR_MEASUREMENT_RD_SIZE)
                return -EOVERFLOW;
 
        buf->tx[0] = cmd;
-       xfer.tx_buf = buf->tx;
-       xfer.rx_buf = data->buffer;
-       xfer.len = pkt_len;
 
-       return spi_sync_transfer(spi, &xfer, 1);
+       /*
+        * Dummy transfer with no data, just cause a 2.5us+ delay between the CS assert
+        * and the first clock edge as per the datasheet tHDSS timing requirement.
+        */
+       xfers[0].delay.value = 2500;
+       xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
+
+       xfers[1].tx_buf = buf->tx;
+       xfers[1].rx_buf = data->buffer;
+       xfers[1].len = pkt_len;
+
+       return spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers));
 }
 
 static const struct mpr_ops mpr_spi_ops = {