clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries

The RZ/G2L SoC family requires DMA resets to be deasserted for routing
some peripheral interrupts to the CPU. Asserting these resets after boot
would silently break interrupt delivery with no driver to restore them.

Mark the DMA resets as critical by adding them to the crit_resets table
in the SoC-specific rzg2l_cpg_info for r9a07g043, r9a07g044, and
r9a08g045, preventing __rzg2l_cpg_assert() from asserting them and
ensuring they are deasserted during probe and resume.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260324114329.268249-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 33e9a1223c7214b39fec31a5f082899f380edf11..70944ef8c5b863aeac201d0bfc32ebcbd619ce3b 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
        MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
 };
 
+static const unsigned int r9a07g043_crit_resets[] = {
+       R9A07G043_DMAC_ARESETN,
+       R9A07G043_DMAC_RST_ASYNC,
+};
+
 #ifdef CONFIG_ARM64
 static const unsigned int r9a07g043_no_pm_mod_clks[] = {
        MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
@@ -420,5 +425,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
        .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
 #endif
 
+       /* Critical Resets */
+       .crit_resets = r9a07g043_crit_resets,
+       .num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),
+
        .has_clk_mon_regs = true,
 };

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0dd264877b9a73ef8276248ce2d0842a1283a961..2d3487203bf541b81c4c8801f3525acabc16aba8 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
        MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
 };
 
+static const unsigned int r9a07g044_crit_resets[] = {
+       R9A07G044_DMAC_ARESETN,
+       R9A07G044_DMAC_RST_ASYNC,
+};
+
 static const unsigned int r9a07g044_no_pm_mod_clks[] = {
        MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
        MOD_CLK_BASE + R9A07G044_CRU_VCLK,
@@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
        .resets = r9a07g044_resets,
        .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
 
+       /* Critical Resets */
+       .crit_resets = r9a07g044_crit_resets,
+       .num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
+
        .has_clk_mon_regs = true,
 };
 #endif
@@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
        .resets = r9a07g044_resets,
        .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
 
+       /* Critical Resets */
+       .crit_resets = r9a07g044_crit_resets,
+       .num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
+
        .has_clk_mon_regs = true,
 };
 #endif

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 79e7b19c788278060606d46761ce6e0f181e9437..1232fec913eb5a2e2f91012dd5811070b247ef8a 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
        MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
 };
 
+static const unsigned int r9a08g045_crit_resets[] = {
+       R9A08G045_DMAC_ARESETN,
+       R9A08G045_DMAC_RST_ASYNC,
+};
+
 static const unsigned int r9a08g045_no_pm_mod_clks[] = {
        MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
 };
@@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
        .resets = r9a08g045_resets,
        .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
 
+       /* Critical Resets */
+       .crit_resets = r9a08g045_crit_resets,
+       .num_crit_resets = ARRAY_SIZE(r9a08g045_crit_resets),
+
        .has_clk_mon_regs = true,
 };