imx8mq: phanbell: enable SPL DM

Switch the Phanbell i.MX8MQ SPL to full Driver Model (DM) boot flow by
moving early device initialization into devicetree and enabling the
required SPL DM subsystems.

Mark GPIO, USDHC, pinctrl, and regulator nodes with bootph-pre-ram so
they are available during SPL. With DM handling MMC and power rails,
remove legacy board-specific USDHC, GPIO, and pad setup code from SPL.

Update the SPL initialization sequence to use spl_early_init(), clears
BSS earlier, and explicitly enables USDHC clocks before handing off to
board_init_r().

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
index 05f809c035d65af2bed512a8a4a7c3da449b269d..11b81f0bbb9bf90e1f3754b352289ae0a4bd3bf0 100644 (file)
--- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
@@ -2,7 +2,12 @@
 
 #include "imx8mq-u-boot.dtsi"
 
+&gpio2 {
+       bootph-pre-ram;
+};
+
 &reg_usdhc2_vmmc {
+       bootph-pre-ram;
        u-boot,off-on-delay-us = <20000>;
 };
 
@@ -13,3 +18,39 @@
 &pinctrl_uart1 {
        bootph-pre-ram;
 };
+
+&usdhc1 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+       bootph-pre-ram;
+};
+
+&usdhc2 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+       bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+       bootph-pre-ram;
+};

diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c
index 642167bca59632ec74c4ab9df946fca5285ed33b..f3aae9256c1cfb4b14812cf476e9571e09d1c667 100644 (file)
--- a/board/google/imx8mq_phanbell/spl.c
+++ b/board/google/imx8mq_phanbell/spl.c
@@ -6,22 +6,13 @@
 
 #include <config.h>
 #include <hang.h>
-#include <asm/io.h>
 #include <errno.h>
 #include <init.h>
 #include <log.h>
-#include <asm/io.h>
 #include <asm/arch/ddr.h>
-#include <asm/arch/imx8mq_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/clock.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/sections.h>
-#include <linux/delay.h>
-#include <fsl_esdhc_imx.h>
-#include <mmc.h>
 #include <spl.h>
 
 static void spl_dram_init(void)
@@ -30,107 +21,6 @@ static void spl_dram_init(void)
        ddr_init(&dram_timing);
 }
 
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
-#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
-#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-       int ret = 0;
-
-       switch (cfg->esdhc_base) {
-       case USDHC1_BASE_ADDR:
-               ret = 1;
-               break;
-       case USDHC2_BASE_ADDR:
-               ret = !gpio_get_value(USDHC2_CD_GPIO);
-               return ret;
-       }
-
-       return 1;
-}
-
-#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
-                        PAD_CTL_FSEL2)
-#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-       IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-       IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
-       IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
-       IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
-       IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
-       {USDHC1_BASE_ADDR},
-       {USDHC2_BASE_ADDR},
-};
-
-int board_mmc_init(struct bd_info *bis)
-{
-       int i, ret;
-       /*
-        * According to the board_mmc_init() the following map is done:
-        * (U-Boot device node)    (Physical Port)
-        * mmc0                    USDHC1
-        * mmc1                    USDHC2
-        */
-       for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
-               switch (i) {
-               case 0:
-                       init_clk_usdhc(0);
-                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
-                       usdhc_cfg[0].max_bus_width = 8;
-                       imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
-                                                        ARRAY_SIZE(usdhc1_pads));
-                       gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
-                       gpio_direction_output(USDHC1_PWR_GPIO, 0);
-                       udelay(500);
-                       gpio_direction_output(USDHC1_PWR_GPIO, 1);
-                       break;
-               case 1:
-                       init_clk_usdhc(1);
-                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
-                       usdhc_cfg[1].max_bus_width = 4;
-                       imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
-                                                        ARRAY_SIZE(usdhc2_pads));
-                       gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
-                       gpio_direction_output(USDHC2_PWR_GPIO, 0);
-                       udelay(500);
-                       gpio_direction_output(USDHC2_PWR_GPIO, 1);
-                       break;
-               default:
-                       printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
-                       return -EINVAL;
-               }
-
-               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
 void spl_board_init(void)
 {
        puts("Normal Boot\n");
@@ -150,6 +40,9 @@ void board_init_f(ulong dummy)
 {
        int ret;
 
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
        arch_cpu_init();
 
        init_uart_clk(0);
@@ -160,12 +53,9 @@ void board_init_f(ulong dummy)
 
        preloader_console_init();
 
-       /* Clear the BSS. */
-       memset(__bss_start, 0, __bss_end - __bss_start);
-
-       ret = spl_init();
+       ret = spl_early_init();
        if (ret) {
-               debug("spl_init() failed: %d\n", ret);
+               debug("spl_early_init() failed: %d\n", ret);
                hang();
        }
 
@@ -174,5 +64,8 @@ void board_init_f(ulong dummy)
        /* DDR initialization */
        spl_dram_init();
 
+       init_clk_usdhc(0);
+       init_clk_usdhc(1);
+
        board_init_r(NULL, 0);
 }

diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index 4c95363ad07c4999968e70f1283051f97c5a0093..07354a786299092aabe8eb3bf0549b33a37d29ed 100644 (file)
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
 CONFIG_TARGET_IMX8MQ_PHANBELL=y
@@ -18,7 +15,7 @@ CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x180000
@@ -67,16 +64,17 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_MMC_DEVICE_INDEX=1
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="FEC"
+CONFIG_SPL_DM=y
 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
@@ -84,13 +82,16 @@ CONFIG_PHY_GIGE=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8M_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_DM_THERMAL=y