serial: qcom-geni: move clock-rate logic to separate function

Facilitates future modifications within the new function,
leading to better readability and maintainability of the code.

Move the code that handles the actual logic of clock-rate
calculations to a separate function geni_serial_set_rate()
which enhances code readability.

Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com>
Link: https://lore.kernel.org/r/20250721174532.14022-7-quic_ptalari@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 45d9735247f83a3b273fca092e44d0be3b9c3350..81f385d900d0612842682f09ee021a1e6ec21622 100644 (file)
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -1314,27 +1314,14 @@ static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
        return ser_clk;
 }
 
-static void qcom_geni_serial_set_termios(struct uart_port *uport,
-                                        struct ktermios *termios,
-                                        const struct ktermios *old)
+static int geni_serial_set_rate(struct uart_port *uport, unsigned int baud)
 {
-       unsigned int baud;
-       u32 bits_per_char;
-       u32 tx_trans_cfg;
-       u32 tx_parity_cfg;
-       u32 rx_trans_cfg;
-       u32 rx_parity_cfg;
-       u32 stop_bit_len;
-       unsigned int clk_div;
-       u32 ser_clk_cfg;
        struct qcom_geni_serial_port *port = to_dev_port(uport);
        unsigned long clk_rate;
-       u32 ver, sampling_rate;
        unsigned int avg_bw_core;
-       unsigned long timeout;
-
-       /* baud rate */
-       baud = uart_get_baud_rate(uport, termios, old, 300, 8000000);
+       unsigned int clk_div;
+       u32 ver, sampling_rate;
+       u32 ser_clk_cfg;
 
        sampling_rate = UART_OVERSAMPLING;
        /* Sampling rate is halved for IP versions >= 2.5 */
@@ -1348,7 +1335,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
                dev_err(port->se.dev,
                        "Couldn't find suitable clock rate for %u\n",
                        baud * sampling_rate);
-               return;
+               return -EINVAL;
        }
 
        dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",
@@ -1370,6 +1357,33 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
        port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
        geni_icc_set_bw(&port->se);
 
+       writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
+       writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
+       return 0;
+}
+
+static void qcom_geni_serial_set_termios(struct uart_port *uport,
+                                        struct ktermios *termios,
+                                        const struct ktermios *old)
+{
+       struct qcom_geni_serial_port *port = to_dev_port(uport);
+       unsigned int baud;
+       unsigned long timeout;
+       u32 bits_per_char;
+       u32 tx_trans_cfg;
+       u32 tx_parity_cfg;
+       u32 rx_trans_cfg;
+       u32 rx_parity_cfg;
+       u32 stop_bit_len;
+       int ret = 0;
+
+       /* baud rate */
+       baud = uart_get_baud_rate(uport, termios, old, 300, 8000000);
+
+       ret = geni_serial_set_rate(uport, baud);
+       if (ret)
+               return;
+
        /* parity */
        tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
        tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
@@ -1437,8 +1451,6 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
        writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
        writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
        writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
-       writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
-       writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
 }
 
 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE