RISC-V: Enable the ZD constraint only when xmipscbop is enabled [PR123092]

The ZD constraint is specific to the mips prefetch instruction.  It is
currently always enabled, leading to ICEs when xmipscbop is disabled.
Solved by only enabling the ZD constraint whenever xmipscbop is enabled.

2026-01-14  Peter Bergner  <bergner@tenstorrent.com>

gcc/
	PR target/123092
	* config/riscv/constraints.md (ZD): Disable when xmipscbop is disabled.

Signed-off-by: Peter Bergner <bergner@tenstorrent.com>

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 85b4fdce5ee05ee1554d29cb4cb63b67326c2af5..673b05954e129b7da625cffbc7e839831a072b99 100644 (file)
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -333,7 +333,7 @@
 
 (define_address_constraint "ZD"
   "An address operand that is valid for a mips prefetch instruction"
-  (match_test "riscv_prefetch_offset_address_p (op, mode)"))
+  (match_test "TARGET_XMIPSCBOP && riscv_prefetch_offset_address_p (op, mode)"))
 
 (define_constraint "Ou07"
   "A 7-bit unsigned immediate."