dmaengine: mediatek: uart-apdma: Fix above 4G addressing TX/RX

The VFF_4G_SUPPORT register is named differently in datasheets,
and its name is "VFF_ADDR2"; was this named correctly from the
beginning it would've been clearer that there was a mistake in
the programming sequence.

This register is supposed to hold the high bits to support the
DMA addressing above 4G (so, more than 32 bits) and not a bit
to "enable" the support for VFF 4G.

Fix the name of this register, and also fix its usage by writing
the upper 32 bits of the dma_addr_t on it when the SoC supports
such feature.

Fixes: 9135408c3ace ("dmaengine: mediatek: Add MediaTek UART APDMA support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251113122229.23998-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/mediatek/mtk-uart-apdma.c b/drivers/dma/mediatek/mtk-uart-apdma.c
index bbacaa89eb920380cdd0301bc897fbb507140c2b..820422cd6942c86b897642cebba81ec6ac469143 100644 (file)
--- a/drivers/dma/mediatek/mtk-uart-apdma.c
+++ b/drivers/dma/mediatek/mtk-uart-apdma.c
@@ -41,7 +41,7 @@
 #define VFF_STOP_CLR_B         0
 #define VFF_EN_CLR_B           0
 #define VFF_INT_EN_CLR_B       0
-#define VFF_4G_SUPPORT_CLR_B   0
+#define VFF_ADDR2_CLR_B                0
 
 /*
  * interrupt trigger level for tx
@@ -72,7 +72,7 @@
 /* TX: the buffer size SW can write. RX: the buffer size HW can write. */
 #define VFF_LEFT_SIZE          0x40
 #define VFF_DEBUG_STATUS       0x50
-#define VFF_4G_SUPPORT         0x54
+#define VFF_ADDR2              0x54
 
 struct mtk_uart_apdmadev {
        struct dma_device ddev;
@@ -149,7 +149,7 @@ static void mtk_uart_apdma_start_tx(struct mtk_chan *c)
                mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
 
                if (mtkd->support_33bits)
-                       mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
+                       mtk_uart_apdma_write(c, VFF_ADDR2, upper_32_bits(d->addr));
        }
 
        mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
@@ -192,7 +192,7 @@ static void mtk_uart_apdma_start_rx(struct mtk_chan *c)
                mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
 
                if (mtkd->support_33bits)
-                       mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
+                       mtk_uart_apdma_write(c, VFF_ADDR2, upper_32_bits(d->addr));
        }
 
        mtk_uart_apdma_write(c, VFF_INT_EN, VFF_RX_INT_EN_B);
@@ -298,7 +298,7 @@ static int mtk_uart_apdma_alloc_chan_resources(struct dma_chan *chan)
        }
 
        if (mtkd->support_33bits)
-               mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B);
+               mtk_uart_apdma_write(c, VFF_ADDR2, VFF_ADDR2_CLR_B);
 
 err_pm:
        pm_runtime_put_noidle(mtkd->ddev.dev);