spi: cadence-qspi: Make sure write protection is disabled

Renesas RZ/N1 QSPI controllers embed the Cadence IP with some
modifications. For instance, they feature a write protection of the
direct mapping at the controller level, with this feature all data
writes to the AHB region are aborted.

Despite the fact that the flag setting write protection is disabled by
default, Bootloaders may (and actually do) set it, so mark this feature
as being available with a specific flag to, if applicable, make sure it
is disabled.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Tested-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://patch.msgid.link/20260122-schneider-6-19-rc1-qspi-v4-12-f9c21419a3e6@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 5df7e6f1bdeaa6f4d49b708e3bafa15c695587c7..8e6b4e21b2cf34d549db116ce1a2fa13fe3ab797 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -48,6 +48,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX);
 #define CQSPI_DISABLE_STIG_MODE                BIT(9)
 #define CQSPI_DISABLE_RUNTIME_PM       BIT(10)
 #define CQSPI_NO_INDIRECT_MODE         BIT(11)
+#define CQSPI_HAS_WR_PROTECT           BIT(12)
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL           BIT(0)
@@ -220,6 +221,8 @@ struct cqspi_driver_platdata {
 #define CQSPI_REG_IRQSTATUS                    0x40
 #define CQSPI_REG_IRQMASK                      0x44
 
+#define CQSPI_REG_WR_PROT_CTRL                 0x58
+
 #define CQSPI_REG_INDIRECTRD                   0x60
 #define CQSPI_REG_INDIRECTRD_START_MASK                BIT(0)
 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK       BIT(1)
@@ -1643,6 +1646,10 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
                       cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
        }
 
+       /* Disable write protection at controller level */
+       if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT)
+               writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL);
+
        /* Disable direct access controller */
        if (!cqspi->use_direct_mode) {
                reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);