media: imx219: Adjust PLL settings based on the number of MIPI lanes

Commit ceddfd4493b3 ("media: i2c: imx219: Support four-lane operation")
added support for device tree to allow configuration of the sensor to
use 4 lanes with a link frequency of 363MHz, and amended the advertised
pixel rate to 280.8MPix/s.

However it didn't change any of the PLL settings, so actually it would
have been running overclocked in the MIPI block, and with the frame
rate and exposure calculations being wrong as the pixel rate was
unchanged.

The pixel rate and link frequency advertised were taken from the "Clock
Setting Example" section of the datasheet. However those are based on an
external clock of 12MHz, and are unachievable with a clock of 24MHz - it
seems PREPLLCLK_VT_DIV and PREPLLCK_OP_DIV can ONLY be set via the
automatic configuration documented in "9-1-2 EXCK_FREQ setting depend on
INCK frequency", not by writing the registers.
The closest we can get with a 24MHz clock is 281.6MPix/s and 364MHz.

Dropping all support for the 363MHz link frequency would cause problems
for existing users, so allow it, but log a warning that the requested
value is being changed to the supported one.

Fixes: ceddfd4493b3 ("media: i2c: imx219: Support four-lane operation")
Cc: stable@vger.kernel.org
Co-developed-by: Peyton Howe <peyton.howe@bellsouth.net>
Signed-off-by: Peyton Howe <peyton.howe@bellsouth.net>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>

diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index c6c30109225c8d2660f61d56abfc87ceb82a008c..64227eb423d4311ebd93a0a0bd8bd17fa12e9623 100644 (file)
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -133,10 +133,11 @@
 
 /* Pixel rate is fixed for all the modes */
 #define IMX219_PIXEL_RATE              182400000
-#define IMX219_PIXEL_RATE_4LANE                280800000
+#define IMX219_PIXEL_RATE_4LANE                281600000
 
 #define IMX219_DEFAULT_LINK_FREQ       456000000
-#define IMX219_DEFAULT_LINK_FREQ_4LANE 363000000
+#define IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED     363000000
+#define IMX219_DEFAULT_LINK_FREQ_4LANE 364000000
 
 /* IMX219 native and active pixel array size. */
 #define IMX219_NATIVE_WIDTH            3296U
@@ -168,15 +169,6 @@ static const struct cci_reg_sequence imx219_common_regs[] = {
        { CCI_REG8(0x30eb), 0x05 },
        { CCI_REG8(0x30eb), 0x09 },
 
-       /* PLL Clock Table */
-       { IMX219_REG_VTPXCK_DIV, 5 },
-       { IMX219_REG_VTSYCK_DIV, 1 },
-       { IMX219_REG_PREPLLCK_VT_DIV, 3 },      /* 0x03 = AUTO set */
-       { IMX219_REG_PREPLLCK_OP_DIV, 3 },      /* 0x03 = AUTO set */
-       { IMX219_REG_PLL_VT_MPY, 57 },
-       { IMX219_REG_OPSYCK_DIV, 1 },
-       { IMX219_REG_PLL_OP_MPY, 114 },
-
        /* Undocumented registers */
        { CCI_REG8(0x455e), 0x00 },
        { CCI_REG8(0x471e), 0x4b },
@@ -201,12 +193,45 @@ static const struct cci_reg_sequence imx219_common_regs[] = {
        { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) },
 };
 
+static const struct cci_reg_sequence imx219_2lane_regs[] = {
+       /* PLL Clock Table */
+       { IMX219_REG_VTPXCK_DIV, 5 },
+       { IMX219_REG_VTSYCK_DIV, 1 },
+       { IMX219_REG_PREPLLCK_VT_DIV, 3 },      /* 0x03 = AUTO set */
+       { IMX219_REG_PREPLLCK_OP_DIV, 3 },      /* 0x03 = AUTO set */
+       { IMX219_REG_PLL_VT_MPY, 57 },
+       { IMX219_REG_OPSYCK_DIV, 1 },
+       { IMX219_REG_PLL_OP_MPY, 114 },
+
+       /* 2-Lane CSI Mode */
+       { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_2_LANE_MODE },
+};
+
+static const struct cci_reg_sequence imx219_4lane_regs[] = {
+       /* PLL Clock Table */
+       { IMX219_REG_VTPXCK_DIV, 5 },
+       { IMX219_REG_VTSYCK_DIV, 1 },
+       { IMX219_REG_PREPLLCK_VT_DIV, 3 },      /* 0x03 = AUTO set */
+       { IMX219_REG_PREPLLCK_OP_DIV, 3 },      /* 0x03 = AUTO set */
+       { IMX219_REG_PLL_VT_MPY, 88 },
+       { IMX219_REG_OPSYCK_DIV, 1 },
+       { IMX219_REG_PLL_OP_MPY, 91 },
+
+       /* 4-Lane CSI Mode */
+       { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_4_LANE_MODE },
+};
+
 static const s64 imx219_link_freq_menu[] = {
        IMX219_DEFAULT_LINK_FREQ,
 };
 
 static const s64 imx219_link_freq_4lane_menu[] = {
        IMX219_DEFAULT_LINK_FREQ_4LANE,
+       /*
+        * This will never be advertised to userspace, but will be used for
+        * v4l2_link_freq_to_bitmap
+        */
+       IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED,
 };
 
 static const char * const imx219_test_pattern_menu[] = {
@@ -662,9 +687,11 @@ static int imx219_set_framefmt(struct imx219 *imx219,
 
 static int imx219_configure_lanes(struct imx219 *imx219)
 {
-       return cci_write(imx219->regmap, IMX219_REG_CSI_LANE_MODE,
-                        imx219->lanes == 2 ? IMX219_CSI_2_LANE_MODE :
-                        IMX219_CSI_4_LANE_MODE, NULL);
+       /* Write the appropriate PLL settings for the number of MIPI lanes */
+       return cci_multi_reg_write(imx219->regmap,
+                                 imx219->lanes == 2 ? imx219_2lane_regs : imx219_4lane_regs,
+                                 imx219->lanes == 2 ? ARRAY_SIZE(imx219_2lane_regs) :
+                                 ARRAY_SIZE(imx219_4lane_regs), NULL);
 };
 
 static int imx219_start_streaming(struct imx219 *imx219,
@@ -1035,6 +1062,7 @@ static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219)
        struct v4l2_fwnode_endpoint ep_cfg = {
                .bus_type = V4L2_MBUS_CSI2_DPHY
        };
+       unsigned long link_freq_bitmap;
        int ret = -EINVAL;
 
        endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
@@ -1056,23 +1084,40 @@ static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219)
        imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes;
 
        /* Check the link frequency set in device tree */
-       if (!ep_cfg.nr_of_link_frequencies) {
-               dev_err_probe(dev, -EINVAL,
-                             "link-frequency property not found in DT\n");
-               goto error_out;
+       switch (imx219->lanes) {
+       case 2:
+               ret = v4l2_link_freq_to_bitmap(dev,
+                                              ep_cfg.link_frequencies,
+                                              ep_cfg.nr_of_link_frequencies,
+                                              imx219_link_freq_menu,
+                                              ARRAY_SIZE(imx219_link_freq_menu),
+                                              &link_freq_bitmap);
+               break;
+       case 4:
+               ret = v4l2_link_freq_to_bitmap(dev,
+                                              ep_cfg.link_frequencies,
+                                              ep_cfg.nr_of_link_frequencies,
+                                              imx219_link_freq_4lane_menu,
+                                              ARRAY_SIZE(imx219_link_freq_4lane_menu),
+                                              &link_freq_bitmap);
+
+               if (!ret && (link_freq_bitmap & BIT(1))) {
+                       dev_warn(dev, "Link frequency of %d not supported, but has been incorrectly advertised previously\n",
+                                IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED);
+                       dev_warn(dev, "Using link frequency of %d\n",
+                                IMX219_DEFAULT_LINK_FREQ_4LANE);
+                       link_freq_bitmap |= BIT(0);
+               }
+               break;
        }
 
-       if (ep_cfg.nr_of_link_frequencies != 1 ||
-          (ep_cfg.link_frequencies[0] != ((imx219->lanes == 2) ?
-           IMX219_DEFAULT_LINK_FREQ : IMX219_DEFAULT_LINK_FREQ_4LANE))) {
+       if (ret || !(link_freq_bitmap & BIT(0))) {
+               ret = -EINVAL;
                dev_err_probe(dev, -EINVAL,
                              "Link frequency not supported: %lld\n",
                              ep_cfg.link_frequencies[0]);
-               goto error_out;
        }
 
-       ret = 0;
-
 error_out:
        v4l2_fwnode_endpoint_free(&ep_cfg);
        fwnode_handle_put(endpoint);