[realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR

Some older RTL8139 chips seem to not immediately update the
RTL_CR.BUFE bit in response to a write to RTL_CAPR.  This results in
iPXE seeing a spurious zero-length received packet, and thereafter
being out of sync with the hardware's RX ring offset.

Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to
give the chip time to react before we next read RTL_CR.

Reported-by: Gelip <mrgelip@gmail.com>
Tested-by: Gelip <mrgelip@gmail.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>

diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c
index d7c4d29d48084db98e3e2275deb04ccaa75d4848..70c0ac1c6096f9c1188cdb547e750e6bf4825b51 100644 (file)
--- a/src/drivers/net/realtek.c
+++ b/src/drivers/net/realtek.c
@@ -861,6 +861,9 @@ static void realtek_legacy_poll_rx ( struct net_device *netdev ) {
                rtl->rx_offset = ( ( rtl->rx_offset + 3 ) & ~3 );
                rtl->rx_offset = ( rtl->rx_offset % RTL_RXBUF_LEN );
                writew ( ( rtl->rx_offset - 16 ), rtl->regs + RTL_CAPR );
+
+               /* Give chip time to react before rechecking RTL_CR */
+               readw ( rtl->regs + RTL_CAPR );
        }
 }