soc: samsung: exynos-pmu: enable CPU hotplug support for gs101

Some additional register writes are required when hotplugging CPUs
on gs101, without these the system hangs when hotplugging.

Specifically a CPU_INFORM register needs to be programmed with
a hint value which is used by the EL3 firmware (el3mon) and the
pmu-intr-gen registers need to be programmed.

With this patch applied, and corresponding DT update CPU hotplug
now works as expected. e.g.

echo 0 > /sys/devices/system/cpu/cpu6/online
echo 1 > /sys/devices/system/cpu/cpu6/online

Note: to maintain compatibility with older DTs that didn't specify
pmu-intr-gen phandle only a warning is issued if the syscon can't
be obtained.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-5-9f64a2657316@linaro.org
[krzk: few blank line and white-space alignment fixes from checkpatch]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index c40313886a012304b3f345d5d7369f15713eb857..a77288f49d249f890060c595556708334383c910 100644 (file)
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -7,6 +7,7 @@
 
 #include <linux/array_size.h>
 #include <linux/arm-smccc.h>
+#include <linux/cpuhotplug.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/mfd/core.h>
@@ -33,6 +34,7 @@ struct exynos_pmu_context {
        struct device *dev;
        const struct exynos_pmu_data *pmu_data;
        struct regmap *pmureg;
+       struct regmap *pmuintrgen;
 };
 
 void __iomem *pmu_base_addr;
@@ -222,7 +224,8 @@ static const struct regmap_config regmap_smccfg = {
 };
 
 static const struct exynos_pmu_data gs101_pmu_data = {
-       .pmu_secure = true
+       .pmu_secure = true,
+       .pmu_cpuhp = true,
 };
 
 /*
@@ -326,6 +329,59 @@ struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np,
 }
 EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle);
 
+/*
+ * CPU_INFORM register hint values which are used by
+ * EL3 firmware (el3mon).
+ */
+#define CPU_INFORM_CLEAR       0
+#define CPU_INFORM_C2          1
+
+static int gs101_cpuhp_pmu_online(unsigned int cpu)
+{
+       unsigned int cpuhint = smp_processor_id();
+       u32 reg, mask;
+
+       /* clear cpu inform hint */
+       regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
+                    CPU_INFORM_CLEAR);
+
+       mask = BIT(cpu);
+
+       regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE,
+                          mask, (0 << cpu));
+
+       regmap_read(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_UPEND, &reg);
+
+       regmap_write(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_CLEAR,
+                    reg & mask);
+
+       return 0;
+}
+
+static int gs101_cpuhp_pmu_offline(unsigned int cpu)
+{
+       u32 reg, mask;
+       unsigned int cpuhint = smp_processor_id();
+
+       /* set cpu inform hint */
+       regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpuhint),
+                    CPU_INFORM_C2);
+
+       mask = BIT(cpu);
+       regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE,
+                          mask, BIT(cpu));
+
+       regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, &reg);
+       regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR,
+                    reg & mask);
+
+       mask = (BIT(cpu + 8));
+       regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, &reg);
+       regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR,
+                    reg & mask);
+       return 0;
+}
+
 static int exynos_pmu_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
@@ -378,6 +434,26 @@ static int exynos_pmu_probe(struct platform_device *pdev)
        pmu_context->pmureg = regmap;
        pmu_context->dev = dev;
 
+       if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_cpuhp) {
+               pmu_context->pmuintrgen = syscon_regmap_lookup_by_phandle(dev->of_node,
+                                                       "google,pmu-intr-gen-syscon");
+               if (IS_ERR(pmu_context->pmuintrgen)) {
+                       /*
+                        * To maintain support for older DTs that didn't specify syscon phandle
+                        * just issue a warning rather than fail to probe.
+                        */
+                       dev_warn(&pdev->dev, "pmu-intr-gen syscon unavailable\n");
+               } else {
+                       cpuhp_setup_state(CPUHP_BP_PREPARE_DYN,
+                                         "soc/exynos-pmu:prepare",
+                                         gs101_cpuhp_pmu_online, NULL);
+
+                       cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+                                         "soc/exynos-pmu:online",
+                                         NULL, gs101_cpuhp_pmu_offline);
+               }
+       }
+
        if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init)
                pmu_context->pmu_data->pmu_init();
 

diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
index 0a49a2c9a08ef5bc75670551bdbf6d0a2d3e8ae9..0938bb4fe15f439e2d8bddeec51b6077e79a7e84 100644 (file)
--- a/drivers/soc/samsung/exynos-pmu.h
+++ b/drivers/soc/samsung/exynos-pmu.h
@@ -22,6 +22,7 @@ struct exynos_pmu_data {
        const struct exynos_pmu_conf *pmu_config;
        const struct exynos_pmu_conf *pmu_config_extra;
        bool pmu_secure;
+       bool pmu_cpuhp;
 
        void (*pmu_init)(void);
        void (*powerdown_conf)(enum sys_powerdown);

diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index ce1a3790d6fb0400021f5cc22394afedfb742152..0d5a17ea8fb81b3ca70627650d5f1768ddc2019a 100644 (file)
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -658,9 +658,20 @@
 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION              (0x32A8)
 
 /* For Tensor GS101 */
+/* PMU ALIVE */
 #define GS101_SYSIP_DAT0                                       (0x810)
+#define GS101_CPU0_INFORM                                      (0x860)
+#define GS101_CPU_INFORM(cpu)  \
+                       (GS101_CPU0_INFORM + (cpu*4))
 #define GS101_SYSTEM_CONFIGURATION                             (0x3A00)
 #define GS101_PHY_CTRL_USB20                                   (0x3EB0)
 #define GS101_PHY_CTRL_USBDP                                   (0x3EB4)
 
+/* PMU INTR GEN */
+#define GS101_GRP1_INTR_BID_UPEND                              (0x0108)
+#define GS101_GRP1_INTR_BID_CLEAR                              (0x010c)
+#define GS101_GRP2_INTR_BID_ENABLE                             (0x0200)
+#define GS101_GRP2_INTR_BID_UPEND                              (0x0208)
+#define GS101_GRP2_INTR_BID_CLEAR                              (0x020c)
+
 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */