]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 9 May 2025 16:01:21 +0000 (17:01 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 10 Jun 2025 08:20:45 +0000 (10:20 +0200)
Add clock and reset entries for GBETH instances. Include core clocks for
PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
used as clock sources for the GBETH IP.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250509160121.331073-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g057-cpg.c
drivers/clk/renesas/rzv2h-cpg.h

index 3c40e36259fe3fc550dcbb2a88bb7b660caa9239..da908e820950b04a713b08e2af63b9a4a74d5560 100644 (file)
@@ -29,6 +29,7 @@ enum clk_ids {
        CLK_PLLDTY,
        CLK_PLLCA55,
        CLK_PLLVDO,
+       CLK_PLLETH,
        CLK_PLLGPU,
 
        /* Internal Core Clocks */
@@ -49,6 +50,14 @@ enum clk_ids {
        CLK_PLLVDO_CRU1,
        CLK_PLLVDO_CRU2,
        CLK_PLLVDO_CRU3,
+       CLK_PLLETH_DIV_250_FIX,
+       CLK_PLLETH_DIV_125_FIX,
+       CLK_CSDIV_PLLETH_GBE0,
+       CLK_CSDIV_PLLETH_GBE1,
+       CLK_SMUX2_GBE0_TXCLK,
+       CLK_SMUX2_GBE0_RXCLK,
+       CLK_SMUX2_GBE1_TXCLK,
+       CLK_SMUX2_GBE1_RXCLK,
        CLK_PLLGPU_GEAR,
 
        /* Module Clocks */
@@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
        {0, 0},
 };
 
+static const struct clk_div_table dtable_2_100[] = {
+       {0, 2},
+       {1, 10},
+       {2, 100},
+       {0, 0},
+};
+
+/* Mux clock tables */
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
+
 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -90,6 +112,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
        DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
        DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
+       DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
        DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
 
        /* Internal Core Clocks */
@@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
        DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
 
+       DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
+       DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
+       DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
+                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
+       DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
+                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
+       DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
+       DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
+       DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
+       DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
+
        DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
 
        /* Core Clocks */
@@ -130,6 +164,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
        DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
        DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
+       DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I,
+                 CLK_PLLETH_DIV_125_FIX, 1, 1),
+       DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I,
+                 CLK_PLLETH_DIV_125_FIX, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
@@ -233,6 +271,30 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(7, BIT(10))),
        DEF_MOD("usb2_0_pclk_usbtst1",          CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
                                                BUS_MSTOP(7, BIT(11))),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD("gbeth_0_aclk_csr_i",           CLK_PLLDTY_DIV8, 11, 12, 5, 28,
+                                               BUS_MSTOP(8, BIT(5))),
+       DEF_MOD("gbeth_0_aclk_i",               CLK_PLLDTY_DIV8, 11, 13, 5, 29,
+                                               BUS_MSTOP(8, BIT(5))),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD("gbeth_1_aclk_csr_i",           CLK_PLLDTY_DIV8, 12, 2, 6, 2,
+                                               BUS_MSTOP(8, BIT(6))),
+       DEF_MOD("gbeth_1_aclk_i",               CLK_PLLDTY_DIV8, 12, 3, 6, 3,
+                                               BUS_MSTOP(8, BIT(6))),
        DEF_MOD("cru_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
                                                BUS_MSTOP(9, BIT(4))),
        DEF_MOD_NO_PM("cru_0_vclk",             CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -304,6 +366,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(10, 13, 4, 30),         /* USB2_0_U2H1_HRESETN */
        DEF_RST(10, 14, 4, 31),         /* USB2_0_U2P_EXL_SYSRST */
        DEF_RST(10, 15, 5, 0),          /* USB2_0_PRESETN */
+       DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
+       DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
        DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
        DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
        DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
index 68c223373916cfba0e645ccfaeda27edc4b2b441..7321b085f937bce65472468fd68d1b4f0b376e74 100644 (file)
@@ -93,6 +93,7 @@ struct smuxed {
                .width = (_width), \
        })
 
+#define CPG_SSEL0              (0x300)
 #define CPG_SSEL1              (0x304)
 #define CPG_CDDIV0             (0x400)
 #define CPG_CDDIV1             (0x404)
@@ -113,8 +114,14 @@ struct smuxed {
 #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
 #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
 
+#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
+#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
 #define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
 
+#define SSEL0_SELCTL2  SMUX_PACK(CPG_SSEL0, 8, 1)
+#define SSEL0_SELCTL3  SMUX_PACK(CPG_SSEL0, 12, 1)
+#define SSEL1_SELCTL0  SMUX_PACK(CPG_SSEL1, 0, 1)
+#define SSEL1_SELCTL1  SMUX_PACK(CPG_SSEL1, 4, 1)
 #define SSEL1_SELCTL2  SMUX_PACK(CPG_SSEL1, 8, 1)
 #define SSEL1_SELCTL3  SMUX_PACK(CPG_SSEL1, 12, 1)