RISC-V: Refactor the test files for all other vector SAT ALU

This patch would like to refactor the all the other testcases of vector
SAT ALU after move to rvv/autovec/sat folder.  Includes:

* Refine the include header files.
* Remove unnecessary optimization options.
* Reconcile the dump check based on option no-opts and/or any-opts.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: Refine
	the include file, remove unnecessary options and reconcile the
	dump check based on options.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Removed.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
index 12d8c01d67f4a4d3cf06301f3b2361bd626b6947..38d105752377f4f4841f863735c52cd77daaf5f1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
index 338e4150f0240ec365a92e60f0086a1df8c43748..b1d0ad03dae3c6629e095f86e14880ef56e68e8d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
index 83ccd4bb86854e174c65e8de448724ecedeec32c..a7cb22d2fb4a3123255879a89a184d18cf6aeff3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
index 06b41046328e65f35fded4732a5bef0f3da40b63..28c24296dab986a45c94d58d0a0b32e4ab8073b0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
index dec0359c5ed9b26e973a3d99f7aff6955d865edf..19c76774a9ce3c6ffc82ed9d27769cc4ad6a0824 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
index 72b2d6778cca53b9e4979e1aae288a6fe1703263..572a4bd112776d599a975da5a926f6a6422a4a6f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
index 3ca44589e42766a228b74eddaa2f9d00f599a282..f41e939cd370cf92d8850ad2db0c12256b82ae69 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
index e3a7bfcf161ca7a0f2219342b758e8ce976be583..af21bf3b85766f89b8844f5ee071fb2a658c2de9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
index c10dc0903c4526b3f3689b8cedd4fd7c490f1062..88304e985fab86a9f41b89abfc29a00342e51ba2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
index d1352ed56e4c629b92935383ee2bf64ecda0470e..f5a312e67f4af81bde4718f091372c29e115baa5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
index b86887d332bfcfb3e6b9cad7a7076dd93dcd314b..3275721528280de3d080d2e7ef90ae0dcae9865d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
index 79ce8dc5d3ec4a3d6c6fe2cd883c5a0c81157796..8b3953f186137f4ff0643eda4c5d7927ea83370b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
index 4497f0c1f83c51dd1e8b2e0363b5e4cc6da50097..7057c6a275e15c2833ec045eb7b586bbe3b7a33a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
index 9f06e6a7650979fea9778b8bc170a66658a202d2..f9c968d6b27c71ce44212cd8d7d8a2e86bfbd2ac 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
index e806fd06c00387253dc8a3c31b088b026d80b839..cd96056d43c0e79a21a3aefca4dbe2849633e71f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
index 254bb18ee3c17b8417526aeb9a66e3a69d549230..24dfbe946394c29cae0cba51c9cbf235f83f1e64 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c
index 7dc8e10ef46887fb1e9dc51f875b3fc2f897a51e..f21061f0a72a836f564afb93ebff616c7a272b49 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c
index b304cd6ea2815db4969a2cd47b422085941b8144..635341e0e05926f77930ea4b9cadd60de5ed52b5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c
index 228c5a88c592d977c2f4ae47b4f1053384b86bcd..bfdf829ca3843623009335b2a9afe7a069deecac 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c
index af408372ba6a9825778d696d44b04b90b4ec65f7..6ea5ae8eb2ec7f88773ccf459b3fd3a6122307e8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c
index 89cd45036d1adc0ff42e02a0ce56d6c24bf43e06..2286e6ae431054e7d7eed3f241e7903bd4621fd4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c
index aa91300111a65e63227a8842f436908f923ca136..051bf7e5de217c2099fadae573e4781f8f846a4e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c
index 061070302323178979860bb25117937acad55e4e..12879ba9588a1a45b9f8ddad14542745590ea0af 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c
index 3b2a24d321e41cc49593f30ffd3142f8634e9ccb..9c5b0a4da2c13a88c7acb93e4a315273aa1b8ded 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c
index 9e26214dab562bbc2f870b772ac84eade243a166..95fac36740b941fa3c2b09128b1111b21eae377c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c
index ed6bc57b59be1aad78c7ad38108f6e9089148393..a35ffb87c81c10d2527205c1df2483ed04e1673a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c
index d62a4a786acd0fdf4f97a6f34daf04e1343d2e4e..d112f272f07e3ed84d869d6474ea325a0f4048a4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c
index 56b0f22825be53e541f56593b41ee882125783b8..ee3c12cbcd3324db54a2b5f5cafed9116c7afe54 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c
index 974fd4054ffeb053ee544b58c3e8122fbd57e542..e12d7d7114624155e93a354fe2d5bda89c74ad4d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c
index 375a59bb6a9af4e07bb8e7e1358b2cf3a5244434..dd17f1857e04556b0b4ff1ccb077ae079570b6bc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c
index 2a301ece90d3bfd20e084c21f80a364a93a4b42e..065245ca597a70e01e634dc3a9fff0c3d1c74d11 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c
index 51dd327994df4dfc0b3668d4ddb32815f2fb1363..a0093072ff1d0dc92853576039f7972df242a8f0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
index dd87dfd0f64edfdc6d55d1f7f60edfb95f773273..51a3b1d065e38f328d6ef0df8d8f1f2aa9341fcb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
index caf646f9520d7cc830ff52f9bc32bcc777503858..95a11e96a66d5a2f298bec775a74419f4babb9eb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX)
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
index f06267a5c474e33a1192384019462b83adb1ffae..1f40a2e8fc7b3bd0a30a2f350e73d461f57894ed 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
index f784937fd482aba471a9808660350fa58426d027..4a5bdfc1fd4a55dd34e491136a805b8af587452a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX)
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
index 1e5289c751c932a928dfe426e0aa8dd31a472655..034bff3b34f3f16422c0174e87b5d1ace3d16eae 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX)
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
index 2fb604b7ddcd288b42fd920bf3f905a106c28fe4..f437c54508c01f30e35b51318524159af7b76749 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
index 3e26e788c083a0add1fa8e5bc08337e8d6eea096..1a0e2d58dbacca05f257748725e33114202ce809 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
index 63797705a04abf86f9272dde89756582433957cf..88bc1f77cc547e58b7b130749759751956056bda 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
index aa996f3e41623ea215993c7216a2acc333cf689a..d56dd050ab26b1f815610409d35e66fac3ccb39b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
index 2a15556632dce2ff4f0e626eec024cd4f0b6962f..db23955415f3314d90edf6cdcad66e7640091966 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
index d9649fc865666e6fb6950a631fd4dbcc7fa0bd94..f9c30fadb48f70857b6dfafa65f5169b6c41a83b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
index 1ad2b3f2546a394669e5d171e8faeb21da1b6c2a..a1b21ab805ede3501321d1b570c394d3e7411d32 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
index 392366def060b2cc466ac37317f028f1447ee58e..933043717608989712c13dc5c548d206be3122c7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
index 2b16049994a5422f412da12926c5e2cea9ad7067..c17b25fd68b1f465bc38cb04f15a5d8dc45cfebb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
index b444d2ea9c64573254309f91ba3dec52f9f810a9..1adc420078cc48c943859209766edf88426396fd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
index 06606581e8fdfa7b4a02e71b7f249ec47d37ff69..b215b4dbd63144becd9cb9af28f095f9612a9525 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
index 72ec727274b2aa05c4421382bf9ae064ec099edf..13e68df011ab2345b4ceff16f0f2632830ef0126 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
index 7915d5417a5137e2df0f51dd7615fcfe68eb6f39..7bd230393e586d2fab7cb13745f78c5d4ff8e40e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
index 2ac96aa1a35b075a893f72388b1585c08bb86984..9b85ac5250fa954f5a1cfd370e69e54a126bd473 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
index 7fe8f277476701bb0316ea8dd96bf794be213ec1..912e2b73526aba836327882b572bb4a67549f085 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
index 96500562cc3cb43fd9dcb19d0eec715efc15907f..f831f79b05f955f45e9f2922252db9ea450e287c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
index b1ed04f0e4e04324844727cff32bcc163829962f..f67afcd4e0985e90d5af1781d96e283812ca67bb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
index 94afc448d07a717b8b99e9381a81cd9f2c6926b1..d0bf273df336f2e2280aa4d7295f2203c026d1fc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
index 483c9e833a74df29224897a70f48184f4f0408f5..d7ea8582184aab3b500c1d875057f665f508d19b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
index 49c076ad2779a77c976b2cf770f0f154456b162b..c62175ecbf750da176bdde794aa674caca03be7e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
index a2a1aa40e017a5c0cb320b40c3d6f89fb2de01fc..0e5fe79d963059eaec35a91df0d02e59d8a0d0dd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
index ba09734efb9163284238f2e6e48c5ee11dbb3990..90f1a3a2f6ce7dd34ba3689c6849624c5b3a8887 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
index 7bc191d03567feaf4890b20fb2b0a26446dcd34f..69f397a90a7d8925f94f10dab29d12c78d4f98dd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
index b896cbea5a68770e61b070f8c5f0dad424257b4a..53a8f86f0f30901eb5f27ef0928c1ab4c735ec1c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
index 67477e5351cae454065155b750a1985a4c0c6d7f..af49f56d1929418ca53b7d546afc41e59b08d7a1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
index c97057355c405b66b90b500c533287d18ff000fd..f2790d8ead08814d8546ab21ba74048fa5e43d44 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
index 629c07347bb9830353888d39f6294778fcd57022..c68eaf7b45ff76b41e62f02dfcabf3a79a008767 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
index c70c8321c06838563920fc47099e45fe3e868724..7f81ee119cf85596db7237519e6e212892773744 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
index d1967baf901d93310e27385e4d6149b2b8793a11..f7da852782456276fbb35d861027ebc56b992325 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
index 8e2625fbed164526df2ed6aae98c1c363faa166d..b3d3d07cc142b99f9120ce8af44b6678c6c80ebf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
index b75a82e342cf8b65c00cb5e2fbce46ce7365789d..c16337cdc682ea77ce443dfe973fb6606195ab1f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
index a6eb2d5b0b2fb6a3d757f371ab14a70d547ed525..171efe722a3200eb140b583d9a9d3ed5d8a39014 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
index fd01c74d2df9ce2598183ae7b5a85c735ab70b8d..9d0e1fdd82d77015a4713e8653553b2cd610c008 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
index 6af61538d59bf2a62370a43f0e834bcacfbaddc5..8175a70239c57304bb0bdbec27f50d64ae69c9d6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
index aee896e3df3e566c69574ce7a12d1bf755f42191..2f6a1ea60ee3cfd4b2d60697431d660a59de96b7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
index ce3ca80e416d4089236da7fc1c7d9b730d8153a2..3862e85b513a9aecd5ac89a8d4e8029d6a164807 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
index b3cb744dd97ea253b5a75e4fa789c94f71dac135..dcde698db485b07cdfa3314b91af1b59b84df7e6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
index 64f140f764e6a09920aa98806106a77322362853..4fc64a281c4804e359d48bde4d4e89053fade352 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
index 9bd95a52a012e347f4e2ab379cbedef28ab2f2c2..c80621a104791a970ffd326788e3bbd03037a721 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
index 0cb9d7796ef4146443aaa2b06d828a37bdff544f..a60ff87c8a7a91f4cfc1a61992d5ce5c698cccf7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
index 8d766e33e88fe6fa2996c7cb8c35861c81a04371..1257dc6427e69918e642b98b80eaa73f3a1a3acc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
index 98ede144020c9eb3f00296a48e4f452fb554645e..9a1fe30bc51b243950b08ae1ac0a11766e126df8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
index 2d9870f6c2b13665d4d3212c13d6454336c25e17..7d6a8e26703d0095bbfc3341f3a7e8ef6f5a4a9f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c
index 508cf348fc9e890fa4c171022a1265708c00a7de..c04a4ce016723d5e9ab2bbfd279a3b16efd76f5c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c
index 3b7c3b6a88216a035ac1063cbe76131528e37bb2..a4eb523868c4466f9883b75f3d97db158fed0190 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c
index 508cf348fc9e890fa4c171022a1265708c00a7de..c04a4ce016723d5e9ab2bbfd279a3b16efd76f5c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c
index 4a049ce679a2f2dc5ca6a505f6c0e295acda79ba..814ca8972e25ee4ee730d21ab7c68b0470eb7112 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c
index 15b6670b1c8552f6b241e37c306ccf34c4ba7fad..8540ca0534708823935cffb04200a6633957b9c5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c
index 5a1dd857b440c9619726f6a0db06d5ad44474f1d..d15ba0ada716e32c8f0a482714ef5752fa848af6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c
index a98447de11f788ac8ffba694a56814d81b13e9a6..0be8714d96a3da9ded02b4ef75679a0b4afa0c15 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c
index 93f40b674fd82f744901414ae6909006ea4cc10a..2691d118ecdbdcfe9700ad6002fbd60a7f298f3f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c
index a98447de11f788ac8ffba694a56814d81b13e9a6..0be8714d96a3da9ded02b4ef75679a0b4afa0c15 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c
index c946ac32264488abeeddc373c3f3f65bc668a4c4..b9d0483eaa9fa9123a51ea7fb9aa63ba2c883c87 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c
index 1d3b03471f9c9b8510d4d16fcee93e2e3a7dc1e7..97fd9aef2b99265256b00a46ef3a2c259829ee9c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c
index 98a637e91e708993fa59e828db7d74423998fad9..1798ef6fbae2bb061d1d5d43d903dbb58f1d60c1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c
index 0b658f3d0aa8ad71b77fc0c92efd4e7721683885..bf84ce0b22402d7b211ce222630c327dd067262a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c
index 41e1789dd62a05809e985724bfe48a6d70de4814..cbaeb83fe68491f0f167f574573b26a8b609fd35 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c
index 0b658f3d0aa8ad71b77fc0c92efd4e7721683885..bf84ce0b22402d7b211ce222630c327dd067262a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c
index 28cd5c806f93c794ebf997ed6b362f4f608ae4ec..7004c369a817fbf7e63b2d48e1c7e13fc1c817d1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c
index a6501f93df7092fc678e015cfa3a7c9ec738d6c1..43cff846d71e0a42195ffe4e0a6d677b9d7e600c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c
index eef36e8dbdb665389c9a3f09e34aa364e6627ada..e1455615b72ad32eb8f56fdab7d925d101307508 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c
index d07b736f5e731684b0e8d50bac0819901351c17b..e3f3584010d0a4bdb8f7dad67fd333d43d139f69 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c
index 06afa3fff686ed5673abd334eaefac0b212000ee..5e36e39d468749c87d3d3478d993fbb376ccc2fb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c
index d07b736f5e731684b0e8d50bac0819901351c17b..e3f3584010d0a4bdb8f7dad67fd333d43d139f69 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c
index de26b5cec1bfcc20352fcebfac2092d8f9d8655d..cbfac223a219a562a2488d7eb6355d2ddfd219ba 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c
index c1907f7d87a1a9889d7e8ede2374e32af905bfad..e5fad5287d78a4fce0357ffaa771e8a71d426546 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c
index 645d7648ab59ca129896e7e3a56e101ec14ff6a2..480ff99ed4e631fc5ca6c33b18b05b135462be7e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c
index c2b7b7b128981cb0312537bc7a6f90c1dd42024c..b924cc82ced8d4087444b783b2ac2bb9086851d5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c
index 238e0d76c34e18fa93e9e328939502265f27177c..1751bcb15783417eb538823f50722d3c532046d2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c
index c2b7b7b128981cb0312537bc7a6f90c1dd42024c..b924cc82ced8d4087444b783b2ac2bb9086851d5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c
index e5ef086c65a287c825c24217c54d8c6a0d1ab1c8..3d9ddd6a29229e87949773ed2a929d8226631e59 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c
index 61158efdcc9bae8d60a40332411db57cf19899d1..84dc7282591695238e2fc91e2571e0978e54f8fe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c
index b688c1190fc55a89ab53f3a8f398763c9083873f..1a0133dd608c3f291444eb311e64571d018b7ad3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c
index 457abd6ee078ab37b6bc2db8eadc5c6212d082da..7c7f404c9e0bcbe40dc5c69dc5238a3b1dfb70d2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c
index 694a771689c39085602512c22901a95f917a4f44..34a07b98e1512fe529383ab80b70b83ed7e54e4b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c
index 457abd6ee078ab37b6bc2db8eadc5c6212d082da..7c7f404c9e0bcbe40dc5c69dc5238a3b1dfb70d2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c
index 6fb64a3e5ffd0208a405db6917daaf7e1501aed4..bb8058dd411a67a15d27b032a23b6f91787c277c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c
index 0c8bc7458ae3f83c1095470cf68845941e0eb962..a9929c733dda41f8d6e0455c0c50fa71d7eddaf5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c
index 3c4513cad758ca4e2efde4dc82786d36e01c5fa6..87634e51496c2562bac588869ab37fea24d3d749 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c
index 53c046436eafe1284aea05f81a55393c2a4b1e06..2f1e111649a9895948ffbcc31f56b6945514b461 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c
index 132de83458d9e40bc52acee9aa7028161d96e42a..55ca0cdebcfe0de3bda05bad64c4c7b505be4fb4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c
index 53c046436eafe1284aea05f81a55393c2a4b1e06..2f1e111649a9895948ffbcc31f56b6945514b461 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c
index 3747149cdb78840aada32bd68137dc31b642a27c..09e08abf65bca875a0bdd96249573de943fdac7a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c
index 8a85d40dc083dcadbc9a02e29f0e7029587a67da..98dc64d36013188b5bf4b5434f9319f0a1060c51 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c
index 11f758ffda3610cf490f07e02652367e4c578da9..2a157468025e67a7fa695445d2201a9834e7242c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c
index 4964599d5456dc955e604c5b393ee09c4e02b07c..e36aeedef11fd78c4cf90977c74ec2d747e726b5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c
index 6c424b2bfa0c24943b59f9daa3b2856616fa8c61..158f00eee794370f976d2ac1695a9c4fb4931d32 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c
index 4964599d5456dc955e604c5b393ee09c4e02b07c..e36aeedef11fd78c4cf90977c74ec2d747e726b5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c
index e7b6cdb9c947ff98af1c89e77c051fec3fe75f9d..57d9b47f041cde370cbf8150553f46ada5455950 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c
index 02456e900f9d4b87f78678d7b720d29375869ee2..730ef4e21b6466de36a0c5e5263dde6b7d025ed8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c
index 23cc7f0248ec3f1b7681ca7eba06419e90813f8f..56fa74bf84ee9c1cd8f3cf44c0413d19d502b48b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c
index 63d2391a63ea3a59fa8c59c9deef5ba3cbee3d2c..972629adac941979a98886cd0480c04bc2a15955 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
index 16ff0c63e5a71cadd7bfa62e4b592c27d091c81f..51f1ee505f616de5dbf95ef06a884bba4a046f26 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
@@ -1,10 +1,20 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
-/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
-/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 6 "expand" { target { any-opts
+     "-mrvv-vector-bits=scalable"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 3 { target { any-ops
+     "-mrvv-vector-bits=scalable"
+   } } } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 2 { target { any-ops
+     "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
deleted file mode 100644 (file)
index cb41955..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ /dev/null
@@ -1,886 +0,0 @@
-#ifndef HAVE_VEC_SAT_ARITH
-#define HAVE_VEC_SAT_ARITH
-
-#include <stdint-gcc.h>
-#include <stdbool.h>
-
-#define VALIDATE_RESULT(out, expect, N)              \
-  do                                                 \
-    {                                                \
-      for (unsigned i = 0; i < N; i++)               \
-        if (out[i] != expect[i]) __builtin_abort (); \
-    }                                                \
-  while (false)
-
-/******************************************************************************/
-/* Saturation Add (unsigned and signed)                                       */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_ADD_FMT_1(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (x + y) | (-(T)((T)(x + y) < x));                     \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_2(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (T)(x + y) >= x ? (x + y) : -1;                       \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_3(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      T overflow = __builtin_add_overflow (x, y, &ret);              \
-      out[i] = (T)(-overflow) | ret;                                 \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_4(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;       \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_5(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1;  \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_6(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x <= (T)(x + y) ? (x + y) : -1;                       \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_7(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (T)(x + y) < x ? -1 : (x + y);                        \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_8(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x > (T)(x + y) ? -1 : (x + y);                        \
-    }                                                                \
-}
-
-#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_7(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_7(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)                          \
-T __attribute__((noinline))                                          \
-vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1;         \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)                          \
-T __attribute__((noinline))                                          \
-vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM);          \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM)                          \
-T __attribute__((noinline))                                          \
-vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  T ret;                                                             \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \
-    }                                                                \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM)                               \
-T __attribute__((noinline))                                               \
-vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit)      \
-{                                                                         \
-  unsigned i;                                                             \
-  T ret;                                                                  \
-  for (i = 0; i < limit; i++)                                             \
-    {                                                                     \
-      out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \
-    }                                                                     \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_2(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_3(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_4(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N)
-
-#define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum = (UT)x + (UT)y;                                         \
-      out[i] = (x ^ y) < 0                                           \
-        ? sum                                                        \
-        : (sum ^ x) >= 0                                             \
-          ? sum                                                      \
-          : x < 0 ? MIN : MAX;                                       \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_1_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum = (UT)x + (UT)y;                                         \
-      if ((x ^ y) < 0 || (sum ^ x) >= 0)                             \
-        out[i] = sum;                                                \
-      else                                                           \
-        out[i] = x < 0 ? MIN : MAX;                                  \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_2_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum;                                                         \
-      bool overflow = __builtin_add_overflow (x, y, &sum);           \
-      out[i] = overflow ? x < 0 ? MIN : MAX : sum;                   \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum;                                                         \
-      bool overflow = __builtin_add_overflow (x, y, &sum);           \
-      out[i] = !overflow ? sum : x < 0 ? MIN : MAX;                  \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_4_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)
-
-#define RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_1(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_1_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_2(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_3(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_4(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N)
-
-/******************************************************************************/
-/* Saturation Sub (Unsigned and Signed)                                       */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_SUB_FMT_1(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (x - y) & (-(T)(x >= y));                             \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_2(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (x - y) & (-(T)(x > y));                              \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_3(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x > y ? x - y : 0;                                    \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_4(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x >= y ? x - y : 0;                                   \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_5(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x < y ? 0 : x - y;                                    \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_6(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x <= y ? 0 : x - y;                                   \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_7(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      T overflow = __builtin_sub_overflow (x, y, &ret);              \
-      out[i] = ret & (T)(overflow - 1);                              \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_8(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      T overflow = __builtin_sub_overflow (x, y, &ret);              \
-      out[i] = ret & (T)-(!overflow);                                \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_9(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      bool overflow = __builtin_sub_overflow (x, y, &ret);           \
-      out[i] = overflow ? 0 : ret;                                   \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_10(T)                                   \
-void __attribute__((noinline))                                        \
-vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      T x = op_1[i];                                                  \
-      T y = op_2[i];                                                  \
-      T ret;                                                          \
-      bool overflow = __builtin_sub_overflow (x, y, &ret);            \
-      out[i] = !overflow ? ret : 0;                                   \
-    }                                                                 \
-}
-
-#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2)                             \
-void __attribute__((noinline))                                    \
-vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
-{                                                                 \
-  T2 a;                                                           \
-  T1 *p = x;                                                      \
-  do {                                                            \
-    a = *--p;                                                     \
-    *p = (T1)(a >= b ? a - b : 0);                                \
-  } while (--limit);                                              \
-}
-#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2)
-
-#define DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM) \
-void __attribute__((noinline))             \
-vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit)  \
-{                                                   \
-  unsigned i;                                       \
-  for (i = 0; i < limit; i++)                       \
-    out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0;  \
-}
-
-#define DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM)
-
-#define RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_sub_imm##IMM##_##T##_fmt_1(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N)
-
-#define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus = (UT)x - (UT)y;                                       \
-      out[i] = (x ^ y) >= 0                                          \
-        ? minus                                                      \
-        : (minus ^ x) >= 0                                           \
-          ? minus                                                    \
-          : x < 0 ? MIN : MAX;                                       \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_1_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus = (UT)x - (UT)y;                                       \
-      out[i] = (x ^ y) >= 0 || (minus ^ x) >= 0                      \
-        ? minus : x < 0 ? MIN : MAX;                                 \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_2_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus;                                                       \
-      bool overflow = __builtin_sub_overflow (x, y, &minus);         \
-      out[i] = overflow ? x < 0 ? MIN : MAX : minus;                 \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_3_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus;                                                       \
-      bool overflow = __builtin_sub_overflow (x, y, &minus);         \
-      out[i] = !overflow ? minus : x < 0 ? MIN : MAX;                \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_4_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MAX)
-
-#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_2(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
-  vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N)
-#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \
-  RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
-
-#define RUN_VEC_SAT_S_SUB_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_1(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_1(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_2(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_SUB_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_3(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_3(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_SUB_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_4(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_4(T, out, op_1, op_2, N)
-
-/******************************************************************************/
-/* Saturation Sub Truncated (Unsigned and Signed)                             */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T)                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_trunc_##OUT_T##_fmt_1 (OUT_T *out, IN_T *op_1, IN_T y, \
-                                    unsigned limit)                 \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      IN_T x = op_1[i];                                              \
-      out[i] = (OUT_T)(x >= y ? x - y : 0);                          \
-    }                                                                \
-}
-
-#define RUN_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T, out, op_1, y, N) \
-  vec_sat_u_sub_trunc_##OUT_T##_fmt_1(out, op_1, y, N)
-
-/******************************************************************************/
-/* Saturation Truncation (Unsigned and Signed)                                */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      bool overflow = x > (WT)(NT)(-1);                               \
-      out[i] = ((NT)x) | (NT)-overflow;                               \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT)
-
-#define DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT max = (WT)(NT)-1;                                            \
-      out[i] = in[i] > max ? (NT)max : (NT)in[i];                     \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_2_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT)
-
-#define DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT max = (WT)(NT)-1;                                            \
-      out[i] = in[i] <= max ? (NT)in[i] : (NT)max;                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT)
-
-#define DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      bool not_overflow = in[i] <= (WT)(NT)(-1);                      \
-      out[i] = ((NT)in[i]) | (NT)((NT)not_overflow - 1);              \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN <= x && x <= (WT)NT_MAX                     \
-       ? trunc                                                       \
-       : x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN < x && x < (WT)NT_MAX                       \
-       ? trunc                                                       \
-       : x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN < x && x <= (WT)NT_MAX                      \
-       ? trunc                                                       \
-       : x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN <= x && x < (WT)NT_MAX                      \
-       ? trunc                                                       \
-       : x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN > x || x > (WT)NT_MAX                       \
-       ? x < 0 ? NT_MIN : NT_MAX                                     \
-       : trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN >= x || x > (WT)NT_MAX                      \
-       ? x < 0 ? NT_MIN : NT_MAX                                     \
-       : trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_7 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN > x || x >= (WT)NT_MAX                      \
-       ? x < 0 ? NT_MIN : NT_MAX                                     \
-       : trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_8 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN >= x || x >= (WT)NT_MAX                     \
-       ? x < 0 ? NT_MIN : NT_MAX                                     \
-       : trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_2(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_2 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_2(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_3(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_3 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_3(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_4 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_1 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_2 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_3 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_4 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_5 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_6 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_7 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_8 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N)
-
-#endif