The fib_entries attribute is a device specific constant.
Therefore move it into the configuration structure. Add
a comment why someone used 16K fib_entries for RTL931x
instead of the possible 32K.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
case RTL8380_FAMILY_ID:
priv->ds->ops = &rtldsa_83xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
- priv->fib_entries = 8192;
priv->ds->num_lag_ids = 8;
priv->l2_bucket_size = 4;
priv->n_mst = 64;
case RTL8390_FAMILY_ID:
priv->ds->ops = &rtldsa_83xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
- priv->fib_entries = 16384;
priv->ds->num_lag_ids = 16;
priv->l2_bucket_size = 4;
priv->n_mst = 256;
case RTL9300_FAMILY_ID:
priv->ds->ops = &rtldsa_93xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
- priv->fib_entries = 16384;
priv->ds->num_lag_ids = 16;
sw_w32(0, RTL930X_ST_CTRL);
priv->l2_bucket_size = 8;
case RTL9310_FAMILY_ID:
priv->ds->ops = &rtldsa_93xx_switch_ops;
priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
- priv->fib_entries = 16384;
priv->ds->num_lag_ids = 16;
sw_w32(0, RTL931x_ST_CTRL);
priv->l2_bucket_size = 8;
mutex_lock(&priv->reg_mutex);
- for (int i = 0; i < priv->fib_entries; i++) {
+ for (int i = 0; i < priv->r->fib_entries; i++) {
bucket = i >> 2;
index = i & 0x3;
priv->r->read_l2_entry_using_hash(bucket, index, &e);
mutex_lock(&priv->reg_mutex);
- for (int i = 0; i < priv->fib_entries; i++) {
+ for (int i = 0; i < priv->r->fib_entries; i++) {
priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
if (!e.valid)
const struct rtldsa_config rtldsa_838x_cfg = {
.cpu_port = RTL838X_CPU_PORT,
+ .fib_entries = 8192,
.mask_port_reg_be = rtl838x_mask_port_reg,
.set_port_reg_be = rtl838x_set_port_reg,
.get_port_reg_be = rtl838x_get_port_reg,
int n_pie_blocks;
u8 cpu_port;
u8 port_ignore;
+ u32 fib_entries;
int trk_ctrl;
int trk_hash_ctrl;
void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
struct mii_bus *parent_bus;
const struct rtldsa_config *r;
u64 irq_mask;
- u32 fib_entries;
int l2_bucket_size;
u16 n_mst;
struct dentry *dbgfs_dir;
const struct rtldsa_config rtldsa_839x_cfg = {
.cpu_port = RTL839X_CPU_PORT,
+ .fib_entries = 16384,
.mask_port_reg_be = rtl839x_mask_port_reg_be,
.set_port_reg_be = rtl839x_set_port_reg_be,
.get_port_reg_be = rtl839x_get_port_reg_be,
const struct rtldsa_config rtldsa_930x_cfg = {
.cpu_port = RTL930X_CPU_PORT,
+ .fib_entries = 16384,
.mask_port_reg_be = rtl838x_mask_port_reg,
.set_port_reg_be = rtl838x_set_port_reg,
.get_port_reg_be = rtl838x_get_port_reg,
const struct rtldsa_config rtldsa_931x_cfg = {
.cpu_port = RTL931X_CPU_PORT,
+ .fib_entries = 16384, /* TODO: has 32K but code cannot handle that */
.mask_port_reg_be = rtl839x_mask_port_reg_be,
.set_port_reg_be = rtl839x_set_port_reg_be,
.get_port_reg_be = rtl839x_get_port_reg_be,