]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
realtek: dsa: move fib_entries to config structure 22438/head
authorMarkus Stockhausen <markus.stockhausen@gmx.de>
Sun, 15 Mar 2026 18:43:08 +0000 (19:43 +0100)
committerHauke Mehrtens <hauke@hauke-m.de>
Tue, 31 Mar 2026 21:35:22 +0000 (23:35 +0200)
The fib_entries attribute is a device specific constant.
Therefore move it into the configuration structure. Add
a comment why someone used 16K fib_entries for RTL931x
instead of the possible 32K.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/debugfs.c
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.h
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c
target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c

index 866728785e4affc65ac0e5b64bcbf84cf3c9f9b3..42790a1423c79b0b5c00f0ab717fc23808fee2b0 100644 (file)
@@ -1610,7 +1610,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
        case RTL8380_FAMILY_ID:
                priv->ds->ops = &rtldsa_83xx_switch_ops;
                priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
-               priv->fib_entries = 8192;
                priv->ds->num_lag_ids = 8;
                priv->l2_bucket_size = 4;
                priv->n_mst = 64;
@@ -1618,7 +1617,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
        case RTL8390_FAMILY_ID:
                priv->ds->ops = &rtldsa_83xx_switch_ops;
                priv->ds->phylink_mac_ops = &rtldsa_83xx_phylink_mac_ops;
-               priv->fib_entries = 16384;
                priv->ds->num_lag_ids = 16;
                priv->l2_bucket_size = 4;
                priv->n_mst = 256;
@@ -1626,7 +1624,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
        case RTL9300_FAMILY_ID:
                priv->ds->ops = &rtldsa_93xx_switch_ops;
                priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
-               priv->fib_entries = 16384;
                priv->ds->num_lag_ids = 16;
                sw_w32(0, RTL930X_ST_CTRL);
                priv->l2_bucket_size = 8;
@@ -1635,7 +1632,6 @@ static int rtl83xx_sw_probe(struct platform_device *pdev)
        case RTL9310_FAMILY_ID:
                priv->ds->ops = &rtldsa_93xx_switch_ops;
                priv->ds->phylink_mac_ops = &rtldsa_93xx_phylink_mac_ops;
-               priv->fib_entries = 16384;
                priv->ds->num_lag_ids = 16;
                sw_w32(0, RTL931x_ST_CTRL);
                priv->l2_bucket_size = 8;
index 2132b4386cdd8e72f686dc4809bb08562b5dba62..4310b470c96ea2a6e9f51f8da3e08fc56a77fa36 100644 (file)
@@ -324,7 +324,7 @@ static int l2_table_show(struct seq_file *m, void *v)
 
        mutex_lock(&priv->reg_mutex);
 
-       for (int i = 0; i < priv->fib_entries; i++) {
+       for (int i = 0; i < priv->r->fib_entries; i++) {
                bucket = i >> 2;
                index = i & 0x3;
                priv->r->read_l2_entry_using_hash(bucket, index, &e);
index 04ae433df5952fb5a266c43719a56f7cfea8ff29..968fbd202ea9bf101af9001f7f476cbc8575ccc1 100644 (file)
@@ -2002,7 +2002,7 @@ static int rtldsa_port_fdb_dump(struct dsa_switch *ds, int port,
 
        mutex_lock(&priv->reg_mutex);
 
-       for (int i = 0; i < priv->fib_entries; i++) {
+       for (int i = 0; i < priv->r->fib_entries; i++) {
                priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
 
                if (!e.valid)
index 1124195844a3672ad23d8d39530243a1517f0b2f..a951b046f7a1831aa6bbbdb87bca410d1c4166b0 100644 (file)
@@ -1808,6 +1808,7 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
 
 const struct rtldsa_config rtldsa_838x_cfg = {
        .cpu_port = RTL838X_CPU_PORT,
+       .fib_entries = 8192,
        .mask_port_reg_be = rtl838x_mask_port_reg,
        .set_port_reg_be = rtl838x_set_port_reg,
        .get_port_reg_be = rtl838x_get_port_reg,
index e62abfdf203fb1fffe867318b8a382299a7b6c06..381141bb0cfa08c41f498ea820b2c23489c0fdab 100644 (file)
@@ -1414,6 +1414,7 @@ struct rtldsa_config {
        int n_pie_blocks;
        u8 cpu_port;
        u8 port_ignore;
+       u32 fib_entries;
        int trk_ctrl;
        int trk_hash_ctrl;
        void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
@@ -1517,7 +1518,6 @@ struct rtl838x_switch_priv {
        struct mii_bus *parent_bus;
        const struct rtldsa_config *r;
        u64 irq_mask;
-       u32 fib_entries;
        int l2_bucket_size;
        u16 n_mst;
        struct dentry *dbgfs_dir;
index c453e70f95f754c8b9d114cbe68eb4fd43f0e838..f1c683d43c0fff2f3e4d1fdabf08e22fc889e3bb 100644 (file)
@@ -1723,6 +1723,7 @@ int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
 
 const struct rtldsa_config rtldsa_839x_cfg = {
        .cpu_port = RTL839X_CPU_PORT,
+       .fib_entries = 16384,
        .mask_port_reg_be = rtl839x_mask_port_reg_be,
        .set_port_reg_be = rtl839x_set_port_reg_be,
        .get_port_reg_be = rtl839x_get_port_reg_be,
index 244bbcdd566a79fde7a28fef915acedc5dc7d2ef..e2fe58b99c4799204f8524668dfec9f69656527a 100644 (file)
@@ -2794,6 +2794,7 @@ static void rtldsa_930x_qos_init(struct rtl838x_switch_priv *priv)
 
 const struct rtldsa_config rtldsa_930x_cfg = {
        .cpu_port = RTL930X_CPU_PORT,
+       .fib_entries = 16384,
        .mask_port_reg_be = rtl838x_mask_port_reg,
        .set_port_reg_be = rtl838x_set_port_reg,
        .get_port_reg_be = rtl838x_get_port_reg,
index 2425a4c2a360129d1068346262b62ea716af4f8f..09f4885bb579a8d25dea53a6dadab00a177339e8 100644 (file)
@@ -1935,6 +1935,7 @@ static void rtldsa_931x_qos_init(struct rtl838x_switch_priv *priv)
 
 const struct rtldsa_config rtldsa_931x_cfg = {
        .cpu_port = RTL931X_CPU_PORT,
+       .fib_entries = 16384, /* TODO: has 32K but code cannot handle that */
        .mask_port_reg_be = rtl839x_mask_port_reg_be,
        .set_port_reg_be = rtl839x_set_port_reg_be,
        .get_port_reg_be = rtl839x_get_port_reg_be,