* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Work around problem

	with some Pentium Ds.

diff --git a/ChangeLog b/ChangeLog
index 4c774652b570aa7e9e6c57bd184223cc999b2995..04615d17db1b46feab1f5080010f9e5b3688fc0f 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2007-10-09  Ulrich Drepper  <drepper@redhat.com>
+
+       * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Work around problem
+       with some Pentium Ds.
+
 2007-10-08  Ulrich Drepper  <drepper@redhat.com>
 
        * sysdeps/unix/sysv/linux/eventfd_read.c (eventfd_read): Use

diff --git a/localedata/locales/de_DE b/localedata/locales/de_DE
index 7f22b22c280affbf99595e45d2082782e2677c27..a694dc28884ebd8a11fd827ee5a5e3af2d1d6032 100644 (file)
--- a/localedata/locales/de_DE
+++ b/localedata/locales/de_DE
@@ -120,7 +120,6 @@ day "<U0053><U006F><U006E><U006E><U0074><U0061><U0067>";/
        "<U0044><U006F><U006E><U006E><U0065><U0072><U0073><U0074><U0061><U0067>";/
        "<U0046><U0072><U0065><U0069><U0074><U0061><U0067>";/
        "<U0053><U0061><U006D><U0073><U0074><U0061><U0067>"
-week    7;19971201;4
 abmon  "<U004A><U0061><U006E>";"<U0046><U0065><U0062>";/
        "<U004D><U00E4><U0072>";"<U0041><U0070><U0072>";/
        "<U004D><U0061><U0069>";"<U004A><U0075><U006E>";/

diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index 5b92bd58491c36edbcda6e9ba994302f8c64a492..12102fea81c0798613cb56d38f98c7b122f1c1a5 100644 (file)
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -456,6 +456,13 @@ init_cacheinfo (void)
               asm volatile ("cpuid"
                            : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
                            : "0" (4), "2" (i++));
+
+             /* There seems to be a bug in at least some Pentium Ds
+                which sometimes fail to iterate all cache parameters.
+                Do not loop indefinitely here, stop in this case and
+                assume there is no such information.  */
+             if ((eax & 0x1f) == 0)
+               goto intel_bug_no_cache_info;
            }
           while (((eax >> 5) & 0x7) != level);
 
@@ -463,6 +470,7 @@ init_cacheinfo (void)
        }
       else
         {
+       intel_bug_no_cache_info:
          /* Assume that all logical threads share the highest cache level.  */
           asm volatile ("cpuid"
                        : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)