nvmem: s32g-ocotp: Add driver for S32G OCOTP

Provide access to the On Chip One-Time Programmable Controller (OCOTP)
pages on the NXP S32G platform.

Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Co-developed-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
Link: https://lore.kernel.org/r/20250912131415.303407-3-srini@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index edd811444ce5f4a1de1c59496f27bec417da2bbc..f3b8ffa77528032d452820ef4441cf6cda85dbf5 100644 (file)
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -240,6 +240,16 @@ config NVMEM_NINTENDO_OTP
          This driver can also be built as a module. If so, the module
          will be called nvmem-nintendo-otp.
 
+config NVMEM_S32G_OCOTP
+       tristate "S32G SoC OCOTP support"
+       depends on ARCH_S32
+       help
+         This is a driver for the 'OCOTP' peripheral available on S32G
+         platforms.
+
+         If you say Y here, you will get support for the One Time
+         Programmable memory pages.
+
 config NVMEM_QCOM_QFPROM
        tristate "QCOM QFPROM Support"
        depends on ARCH_QCOM || COMPILE_TEST

diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 2021d59688dbd58ee6895d36610fe670d9479ef5..5634945f81969ecedee0dc029ba1cf3fadc5b5e1 100644 (file)
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -79,6 +79,8 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP)     += nvmem_sunplus_ocotp.o
 nvmem_sunplus_ocotp-y                  := sunplus-ocotp.o
 obj-$(CONFIG_NVMEM_SUNXI_SID)          += nvmem_sunxi_sid.o
 nvmem_sunxi_sid-y                      := sunxi_sid.o
+obj-$(CONFIG_NVMEM_S32G_OCOTP)         += nvmem-s32g-ocotp-nvmem.o
+nvmem-s32g-ocotp-nvmem-y               := s32g-ocotp-nvmem.o
 obj-$(CONFIG_NVMEM_U_BOOT_ENV)         += nvmem_u-boot-env.o
 nvmem_u-boot-env-y                     := u-boot-env.o
 obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE)     += nvmem-uniphier-efuse.o

diff --git a/drivers/nvmem/s32g-ocotp-nvmem.c b/drivers/nvmem/s32g-ocotp-nvmem.c
new file mode 100644 (file)
index 0000000..119871a
--- /dev/null
+++ b/drivers/nvmem/s32g-ocotp-nvmem.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023-2025 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+struct s32g_ocotp_priv {
+       struct device *dev;
+       void __iomem *base;
+};
+
+static int s32g_ocotp_read(void *context, unsigned int offset,
+                           void *val, size_t bytes)
+{
+       struct s32g_ocotp_priv *s32g_data = context;
+       u32 *dst = val;
+
+       while (bytes >= sizeof(u32)) {
+               *dst++ = ioread32(s32g_data->base + offset);
+
+               bytes -= sizeof(u32);
+               offset += sizeof(u32);
+       }
+
+       return 0;
+}
+
+static struct nvmem_keepout s32g_keepouts[] = {
+       { .start = 0,   .end = 520 },
+       { .start = 540, .end = 564 },
+       { .start = 596, .end = 664 },
+       { .start = 668, .end = 676 },
+       { .start = 684, .end = 732 },
+       { .start = 744, .end = 864 },
+       { .start = 908, .end = 924 },
+       { .start = 928, .end = 936 },
+       { .start = 948, .end = 964 },
+       { .start = 968, .end = 976 },
+       { .start = 984, .end = 1012 },
+};
+
+static struct nvmem_config s32g_ocotp_nvmem_config = {
+       .name = "s32g-ocotp",
+       .add_legacy_fixed_of_cells = true,
+       .read_only = true,
+       .word_size = 4,
+       .reg_read = s32g_ocotp_read,
+       .keepout = s32g_keepouts,
+       .nkeepout = ARRAY_SIZE(s32g_keepouts),
+};
+
+static const struct of_device_id ocotp_of_match[] = {
+       { .compatible = "nxp,s32g2-ocotp" },
+       { /* sentinel */ }
+};
+
+static int s32g_ocotp_probe(struct platform_device *pdev)
+{
+       struct s32g_ocotp_priv *s32g_data;
+       struct device *dev = &pdev->dev;
+       struct nvmem_device *nvmem;
+       struct resource *res;
+
+       s32g_data = devm_kzalloc(dev, sizeof(*s32g_data), GFP_KERNEL);
+       if (!s32g_data)
+               return -ENOMEM;
+
+       s32g_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+       if (IS_ERR(s32g_data->base))
+               return dev_err_probe(dev, PTR_ERR(s32g_data->base),
+                                    "Cannot map OCOTP device.\n");
+
+       s32g_data->dev = dev;
+       s32g_ocotp_nvmem_config.dev = dev;
+       s32g_ocotp_nvmem_config.priv = s32g_data;
+       s32g_ocotp_nvmem_config.size = resource_size(res);
+
+       nvmem = devm_nvmem_register(dev, &s32g_ocotp_nvmem_config);
+
+       return PTR_ERR_OR_ZERO(nvmem);
+}
+
+static struct platform_driver s32g_ocotp_driver = {
+       .probe = s32g_ocotp_probe,
+       .driver = {
+               .name = "s32g-ocotp",
+               .of_match_table = ocotp_of_match,
+       },
+};
+module_platform_driver(s32g_ocotp_driver);
+MODULE_AUTHOR("NXP");
+MODULE_DESCRIPTION("S32G OCOTP driver");
+MODULE_LICENSE("GPL");