#define MAC_VLAN2 0x00000024 /* VLAN2 Tag */
/* MAC CTRL defines */
-#define MAC_CONTROL_RA 0x80000000 /* Receive All Mode */
-#define MAC_CONTROL_BLE 0x40000000 /* Endian Mode */
#define MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */
#define MAC_CONTROL_PS 0x08000000 /* Port Select */
-#define MAC_CONTROL_DRO 0x00800000 /* Disable Receive Own */
-#define MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */
#define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */
#define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */
#define MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */
#define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */
#define MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */
-#define MAC_CONTROL_PB 0x00010000 /* Pass Bad Frames */
#define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */
#define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */
-#define MAC_CONTROL_LCC 0x00001000 /* Late Collision Control */
-#define MAC_CONTROL_DBF 0x00000800 /* Disable Broadcast Frames */
-#define MAC_CONTROL_DRTY 0x00000400 /* Disable Retry */
-#define MAC_CONTROL_ASTP 0x00000100 /* Automatic Pad Stripping */
-#define MAC_CONTROL_BOLMT_10 0x00000000 /* Back Off Limit 10 */
-#define MAC_CONTROL_BOLMT_8 0x00000040 /* Back Off Limit 8 */
-#define MAC_CONTROL_BOLMT_4 0x00000080 /* Back Off Limit 4 */
-#define MAC_CONTROL_BOLMT_1 0x000000c0 /* Back Off Limit 1 */
-#define MAC_CONTROL_DC 0x00000020 /* Deferral Check */
-#define MAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
-#define MAC_CONTROL_RE 0x00000004 /* Receiver Enable */
#define MAC_CORE_INIT (MAC_CONTROL_HBD)
/* MAC FLOW CTRL defines */
#define MAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */
-#define MAC_FLOW_CTRL_PASS 0x00000004 /* Pass Control Frames */
#define MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */
-#define MAC_FLOW_CTRL_PAUSE 0x00000001 /* Flow Control Busy ... */
-
-/* MII ADDR defines */
-#define MAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
-#define MAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
/*----------------------------------------------------------------------------
* DMA BLOCK defines
*---------------------------------------------------------------------------*/
/* DMA Bus Mode register defines */
-#define DMA_BUS_MODE_DBO 0x00100000 /* Descriptor Byte Ordering */
-#define DMA_BUS_MODE_BLE 0x00000080 /* Big Endian/Little Endian */
#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
-#define DMA_BUS_MODE_DSL_MASK GENMASK(6, 2) /* Descriptor Skip Length */
-#define DMA_BUS_MODE_BAR_BUS 0x00000002 /* Bar-Bus Arbitration */
#define DMA_BUS_MODE_DEFAULT 0x00000000
-/* DMA Control register defines */
-#define DMA_CONTROL_SF 0x00200000 /* Store And Forward */
-
/* Transmit Threshold Control */
enum ttc_control {
DMA_CONTROL_TTC_DEFAULT = 0x00000000, /* Threshold is 32 DWORDS */
#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
#define GMAC_DEBUG 0x00000024 /* GMAC debug register */
-#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
-#define GMAC_INT_STATUS_PMT BIT(3)
-#define GMAC_INT_STATUS_MMCIS BIT(4)
#define GMAC_INT_STATUS_MMCRIS BIT(5)
#define GMAC_INT_STATUS_MMCTIS BIT(6)
#define GMAC_INT_STATUS_MMCCSUM BIT(7)
-#define GMAC_INT_STATUS_TSTAMP BIT(9)
#define GMAC_INT_STATUS_LPIIS BIT(10)
/* interrupt mask register */
/* GMAC Configuration defines */
#define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
-#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
-#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */
#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */
#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
-#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
-#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
-#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
-#define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */
-#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
-#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
-#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | \
GMAC_CONTROL_BE | GMAC_CONTROL_DCRS)
/* GMAC Frame Filter defines */
#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
-#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
-#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
-#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
#define GMAC_FRAME_FILTER_PCF 0x00000080 /* Pass Control frames */
-#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
-#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
-/* GMII ADDR defines */
-#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
-#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
/* GMAC FLOW CTRL defines */
#define GMAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */
#define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */
#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
-#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
/* DEBUG Register defines */
/* MTL TxStatus FIFO */
#define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
/* MTL Tx FIFO Read Controller Status */
#define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)
-#define GMAC_DEBUG_TRCSTS_IDLE 0
#define GMAC_DEBUG_TRCSTS_READ 1
#define GMAC_DEBUG_TRCSTS_TXW 2
#define GMAC_DEBUG_TRCSTS_WRITE 3
#define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
/* MAC Transmit Frame Controller Status */
#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
-#define GMAC_DEBUG_TFCSTS_IDLE 0
#define GMAC_DEBUG_TFCSTS_WAIT 1
#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
#define GMAC_DEBUG_TFCSTS_XFER 3
/*--- DMA BLOCK defines ---*/
/* DMA Bus Mode register defines */
-#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */
-#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
-#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
/* Programmable burst length (passed thorugh platform)*/
#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
#define DMA_BUS_MODE_AAL 0x02000000
/* DMA CRS Control and Status Register Mapping */
-#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */
-#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */
-/* DMA Bus Mode register defines */
-#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
-#define DMA_BUS_PR_RATIO_SHIFT 14
-#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
/* Disable Drop TCP/IP csum error */
-#define DMA_CONTROL_DT 0x04000000
#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
/* Threshold for Activating the FC */
#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
#define DMA_CONTROL_EFC 0x00000100
-#define DMA_CONTROL_FEF 0x00000080
-#define DMA_CONTROL_FUF 0x00000040
/* Receive flow control activation field
* RFA field in DMA control register, bits 23,10:9
*/
#define RFA_FULL_MINUS_1K 0x00000000
-#define RFA_FULL_MINUS_2K 0x00000200
-#define RFA_FULL_MINUS_3K 0x00000400
-#define RFA_FULL_MINUS_4K 0x00000600
-#define RFA_FULL_MINUS_5K 0x00800000
-#define RFA_FULL_MINUS_6K 0x00800200
-#define RFA_FULL_MINUS_7K 0x00800400
-
-#define RFD_FULL_MINUS_1K 0x00000000
+
#define RFD_FULL_MINUS_2K 0x00000800
-#define RFD_FULL_MINUS_3K 0x00001000
-#define RFD_FULL_MINUS_4K 0x00001800
-#define RFD_FULL_MINUS_5K 0x00400000
-#define RFD_FULL_MINUS_6K 0x00400800
-#define RFD_FULL_MINUS_7K 0x00401000
enum rtc_control {
DMA_CONTROL_RTC_64 = 0x00000000,
#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */
/* MMC registers offset */
-#define GMAC_MMC_CTRL 0x100
-#define GMAC_MMC_RX_INTR 0x104
-#define GMAC_MMC_TX_INTR 0x108
-#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
#define GMAC_EXTHASH_BASE 0x500
/* PTP and timestamping registers */
#define DMA_SYS_BUS_MODE 0x00001004
-#define DMA_BUS_MODE_SPH BIT(24)
#define DMA_BUS_MODE_PBL BIT(16)
#define DMA_BUS_MODE_RPBL_MASK GENMASK(21, 16)
#define DMA_BUS_MODE_MB BIT(14)
#define DMA_STATUS 0x00001008
-#define DMA_STATUS_MAC BIT(17)
-#define DMA_STATUS_MTL BIT(16)
-#define DMA_STATUS_CHAN7 BIT(7)
-#define DMA_STATUS_CHAN6 BIT(6)
-#define DMA_STATUS_CHAN5 BIT(5)
-#define DMA_STATUS_CHAN4 BIT(4)
-#define DMA_STATUS_CHAN3 BIT(3)
-#define DMA_STATUS_CHAN2 BIT(2)
-#define DMA_STATUS_CHAN1 BIT(1)
-#define DMA_STATUS_CHAN0 BIT(0)
-
-#define DMA_DEBUG_STATUS_0 0x0000100c
-#define DMA_DEBUG_STATUS_1 0x00001010
-#define DMA_DEBUG_STATUS_2 0x00001014
-
-#define DMA_DEBUG_STATUS_TS_MASK 0xf
-#define DMA_DEBUG_STATUS_RS_MASK 0xf
-
#define DMA_AXI_BUS_MODE 0x00001028
#define DMA_AXI_EN_LPI BIT(31)
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
#define DMA_SYS_BUS_MB BIT(14)
-#define DMA_AXI_1KBBE BIT(13)
#define DMA_SYS_BUS_AAL DMA_AXI_AAL
#define DMA_SYS_BUS_EAME BIT(11)
#define DMA_SYS_BUS_FB BIT(0)
-#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
- DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
- DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
- DMA_AXI_BLEN4)
-
#define DMA_TBS_CTRL 0x00001050
#define DMA_TBS_FTOS GENMASK(31, 8)
return addr;
}
-#define DMA_CHAN_REG_NUMBER 17
-
#define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x)
#define DMA_CONTROL_SPH BIT(24)
-#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
#define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4)
#define DMA_CHAN_INTR_ENA_AIE BIT(15)
#define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
#define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
-#define DMA_CHAN_INTR_ENA_CDE BIT(13)
#define DMA_CHAN_INTR_ENA_FBE BIT(12)
-#define DMA_CHAN_INTR_ENA_ERE BIT(11)
-#define DMA_CHAN_INTR_ENA_ETE BIT(10)
-#define DMA_CHAN_INTR_ENA_RWE BIT(9)
-#define DMA_CHAN_INTR_ENA_RSE BIT(8)
-#define DMA_CHAN_INTR_ENA_RBUE BIT(7)
#define DMA_CHAN_INTR_ENA_RIE BIT(6)
-#define DMA_CHAN_INTR_ENA_TBUE BIT(2)
-#define DMA_CHAN_INTR_ENA_TSE BIT(1)
#define DMA_CHAN_INTR_ENA_TIE BIT(0)
#define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
/* Interrupt status per channel */
#define DMA_CHAN_STATUS_REB GENMASK(21, 19)
-#define DMA_CHAN_STATUS_REB_SHIFT 19
-#define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
-#define DMA_CHAN_STATUS_TEB_SHIFT 16
#define DMA_CHAN_STATUS_NIS BIT(15)
#define DMA_CHAN_STATUS_AIS BIT(14)
#define DMA_CHAN_STATUS_CDE BIT(13)
DMA_CHAN_STATUS_TI | \
DMA_CHAN_STATUS_MSK_COMMON)
-#define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
-#define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
-#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
-#define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
-
int dwmac4_dma_reset(void __iomem *ioaddr);
void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 chan, bool rx, bool tx);
#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
#define DMA_STATUS 0x00001014 /* Status Register */
-#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */
#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
-#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
-#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
-#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
#define DMA_STATUS_TS_MASK GENMASK(22, 20) /* Transmit Process State */
#define DMA_STATUS_RS_MASK GENMASK(19, 17) /* Receive Process State */
#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
/* DMA Normal interrupt */
#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
-#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
-#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
DMA_INTR_ENA_TIE)
/* DMA Abnormal interrupt */
#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
-#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
-#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
-#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
-#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
-#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
-#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
-#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
DMA_INTR_ENA_UNE)
#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
-#define DMA_CHAN_MISSED_FRAME_CTR(chan) \
- dma_chan_base_addr(DMA_MISSED_FRAME_CTR, chan)
#define DMA_CHAN_RX_WATCHDOG(chan) \
dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
-#define DMA_AXI_OSR_MAX 0xf
-#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
- (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
-#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
- DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
- DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
- DMA_AXI_BLEN4)
-
#define DMA_AXI_1KBBE BIT(13)
#define DMA_AXI_UNDEF BIT(0)
projects / thirdparty / kernel / linux.git / commitdiff
