Merge rev 1.16.4.8 from ERASER into VALGRIND_1_0_BRANCH:

Added Cyrille Chepelov's patch for identifying cache params of Duron stepping
A0 which has a bug that causes CPUID to misreport L2 cache size.  Untested, I
can only assume it works as I don't have such a machine to try with.

git-svn-id: svn://svn.valgrind.org/valgrind/branches/VALGRIND_1_0_BRANCH@607

diff --git a/vg_cachesim.c b/vg_cachesim.c
index 4f1bf10716b96a50ff2b49ed1a9d351c87f15b94..a60b7765c907132f7e8b33b04bdaccd6d3bc004f 100644 (file)
--- a/vg_cachesim.c
+++ b/vg_cachesim.c
@@ -882,12 +882,16 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
  * #3  The AMD K7 processor's L2 cache must be configured prior to relying 
  *     upon this information. (Whatever that means -- njn)
  *
+ * Also, according to Cyrille Chepelov, Duron stepping A0 processors (model
+ * 0x630) have a bug and misreport their L2 size as 1KB (it's really 64KB),
+ * so we detect that.
+ * 
  * Returns 0 on success, non-zero on failure.
  */
 static
 Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c)
 {
-   Int dummy, ext_level;
+   Int dummy, model, ext_level;
    Int I1i, D1i, L2i;
    
    cpuid(0x80000000, &ext_level, &dummy, &dummy, &dummy);
@@ -902,6 +906,16 @@ Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c)
    cpuid(0x80000005, &dummy, &dummy, &D1i, &I1i);
    cpuid(0x80000006, &dummy, &dummy, &L2i, &dummy);
 
+   cpuid(0x1, &model, &dummy, &dummy, &dummy);
+   /*VG_(message)(Vg_UserMsg,"CPU model %04x",model);*/
+
+   /* Check for Duron bug */
+   if (model == 0x630) {
+      VG_(message)(Vg_UserMsg,
+         "Buggy Duron stepping A0. Assuming L2 size=65536 bytes");
+      L2i = (64 << 16) | (L2i & 0xffff);
+   }
+
    D1c->size      = (D1i >> 24) & 0xff;
    D1c->assoc     = (D1i >> 16) & 0xff;
    D1c->line_size = (D1i >>  0) & 0xff;