+2016-03-29 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Revert
+ 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (insns): Add ARMv8-M security extensions
+ instructions.
+
2016-03-29 Thomas Preud'homme <thomas.preudhomme@arm.com>
Revert
#define ARM_VARIANT NULL
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8m
- TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
- TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
- TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
- TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
- TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
+2016-03-29 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Revert
+ 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * gas/arm/any-cmse.d: Likewise.
+ * gas/arm/archv8m-cmse.s: New file.
+ * gas/arm/archv8m-cmse-base.d: Likewise.
+ * gas/arm/archv8m-cmse-main.d: Likewise.
+
2016-03-29 Thomas Preud'homme <thomas.preudhomme@arm.com>
Revert
+++ /dev/null
-#name: attributes for 'any' CPU with ARMv8-M security extension instructions
-#source: archv8m-cmse.s
-#as:
-#readelf: -A
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
- Tag_CPU_arch: v8-M.baseline
- Tag_CPU_arch_profile: Microcontroller
- Tag_THUMB_ISA_use: Yes
+++ /dev/null
-#name: ARM V8-M baseline instructions
-#source: archv8m-cmse.s
-#as: -march=armv8-m.base
-#objdump: -dr --prefix-addresses --show-raw-insn
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+.* <[^>]*> e97f e97f sg
-0+.* <[^>]*> 47a4 blxns r4
-0+.* <[^>]*> 47cc blxns r9
-0+.* <[^>]*> 4724 bxns r4
-0+.* <[^>]*> 474c bxns r9
-0+.* <[^>]*> e841 f080 tta r0, r1
-0+.* <[^>]*> e849 f880 tta r8, r9
-0+.* <[^>]*> e841 f0c0 ttat r0, r1
-0+.* <[^>]*> e849 f8c0 ttat r8, r9
+++ /dev/null
-#name: ARM V8-M mainline instructions
-#source: archv8m-cmse.s
-#as: -march=armv8-m.main
-#objdump: -dr --prefix-addresses --show-raw-insn
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+.* <[^>]*> e97f e97f sg
-0+.* <[^>]*> 47a4 blxns r4
-0+.* <[^>]*> 47cc blxns r9
-0+.* <[^>]*> 4724 bxns r4
-0+.* <[^>]*> 474c bxns r9
-0+.* <[^>]*> e841 f080 tta r0, r1
-0+.* <[^>]*> e849 f880 tta r8, r9
-0+.* <[^>]*> e841 f0c0 ttat r0, r1
-0+.* <[^>]*> e849 f8c0 ttat r8, r9
+++ /dev/null
-.thumb
-.syntax unified
-
-sg
-blxns r4
-blxns r9
-bxns r4
-bxns r9
-tta r0, r1
-tta r8, r9
-ttat r0, r1
-ttat r8, r9
+2016-03-29 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Revert
+ 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (thumb_opcodes): Add entries for narrow ARMv8-M security
+ extensions instructions.
+ (thumb32_opcodes): Add entries for wide ARMv8-M security extensions
+ instructions.
+
2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Add entries for narrow ARMv8-M security
{
/* Thumb instructions. */
- /* ARM V8-M instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
-
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
static const struct opcode32 thumb32_opcodes[] =
{
/* V8-M instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
- 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
- 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
/* V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),