/**
* DOC: mtype_local (int)
*/
-int amdgpu_mtype_local;
-MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
+int amdgpu_mtype_local = -1;
+MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)");
module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);
/**
mtype_local = is_aid_a1 ? MTYPE_RW : MTYPE_NC;
mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC;
- if (amdgpu_mtype_local == 1) {
+ if (amdgpu_mtype_local == 0) {
+ DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
+ mtype_local = MTYPE_RW;
+ } else if (amdgpu_mtype_local == 1) {
DRM_INFO_ONCE("Using MTYPE_NC for local memory\n");
mtype_local = MTYPE_NC;
} else if (amdgpu_mtype_local == 2) {
- DRM_INFO_ONCE("MTYPE_CC not supported, using MTYPE_RW instead for local memory\n");
+ DRM_INFO_ONCE("MTYPE_CC not supported, using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC");
} else {
- DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
+ DRM_INFO_ONCE("Using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC");
}
is_local = (is_vram && adev == bo_adev);
/* for physically contiguous pages (vram) */
u32 header = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
- if (amdgpu_mtype_local)
- header |= SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x3);
- else
- header |= (SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x2) |
- SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1) |
- SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(0x3));
+ /* TODO:
+ * When VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is enabled, change below MTYPE
+ * to RW for AID A1 and UC for AID A0. NC needs additional GCR flush and need not
+ * be supported. Also, honour amdgpu_mtype_local override. RW would additionally
+ * require setting SCOPE bits in the header.
+ *
+ * header |= (SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x2:RW) |
+ * SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1) |
+ * SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(0x3:SYS_SCOPE));
+ */
+
+ /* VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is 0 which defaults to UC. So,
+ * use MTYPE_UC (0x3). For ref. MTYPE_RW=0x2 MTYPE_NC=0x0
+ */
+ header |= SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x3) | SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1);
ib->ptr[ib->length_dw++] = header;
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
bool is_local = (domain == SVM_RANGE_VRAM_DOMAIN) &&
(bo_node->adev == node->adev);
- mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC :
- is_aid_a1 ?
- AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC;
+ mtype_local = amdgpu_mtype_local == 0 ? AMDGPU_VM_MTYPE_RW :
+ amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC :
+ is_aid_a1 ? AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC;
mtype_remote = is_aid_a1 ? AMDGPU_VM_MTYPE_NC : AMDGPU_VM_MTYPE_UC;
snoop = true;