]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
iommu/arm-smmu-v3: Remove IAS
authorMostafa Saleh <smostafa@google.com>
Fri, 2 Jan 2026 20:53:52 +0000 (20:53 +0000)
committerWill Deacon <will@kernel.org>
Wed, 7 Jan 2026 21:22:33 +0000 (21:22 +0000)
The driver only supports AArch64 page tables where OAS == IAS.

Remove the extra IAS tracking for AArch32 as this feature was
never implemented and that was creating BAD_STEs for SMMUv3
with stage-2 and OAS < 40.

Further discussion on this in:
https://lore.kernel.org/linux-iommu/20251130194506.593700-1-smostafa@google.com/

Reported-by: Tomasz Nowicki <tnowicki@google.com>
Fixes: f0c453dbcce7 ("iommu/arm-smmu: Ensure IAS is set correctly for AArch32-capable SMMUs")
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Signed-off-by: Will Deacon <will@kernel.org>
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

index 7a6aea3b61c115379ef792256baf49f4cd05bf90..62bdc4d39101a3582965df761427c873057860ba 100644 (file)
@@ -2562,7 +2562,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain,
                                     ARM_SMMU_FEAT_VAX) ? 52 : 48;
 
                pgtbl_cfg.ias = min_t(unsigned long, ias, VA_BITS);
-               pgtbl_cfg.oas = smmu->ias;
+               pgtbl_cfg.oas = smmu->oas;
                if (enable_dirty)
                        pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_HD;
                fmt = ARM_64_LPAE_S1;
@@ -2572,7 +2572,7 @@ static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain,
        case ARM_SMMU_DOMAIN_S2:
                if (enable_dirty)
                        return -EOPNOTSUPP;
-               pgtbl_cfg.ias = smmu->ias;
+               pgtbl_cfg.ias = smmu->oas;
                pgtbl_cfg.oas = smmu->oas;
                fmt = ARM_64_LPAE_S2;
                finalise_stage_fn = arm_smmu_domain_finalise_s2;
@@ -4406,13 +4406,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
        }
 
        /* We only support the AArch64 table format at present */
-       switch (FIELD_GET(IDR0_TTF, reg)) {
-       case IDR0_TTF_AARCH32_64:
-               smmu->ias = 40;
-               fallthrough;
-       case IDR0_TTF_AARCH64:
-               break;
-       default:
+       if (!(FIELD_GET(IDR0_TTF, reg) & IDR0_TTF_AARCH64)) {
                dev_err(smmu->dev, "AArch64 table format not supported!\n");
                return -ENXIO;
        }
@@ -4525,8 +4519,6 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
                dev_warn(smmu->dev,
                         "failed to set DMA mask for table walker\n");
 
-       smmu->ias = max(smmu->ias, smmu->oas);
-
        if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) &&
            (smmu->features & ARM_SMMU_FEAT_TRANS_S2))
                smmu->features |= ARM_SMMU_FEAT_NESTING;
@@ -4536,8 +4528,8 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
        if (arm_smmu_sva_supported(smmu))
                smmu->features |= ARM_SMMU_FEAT_SVA;
 
-       dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n",
-                smmu->ias, smmu->oas, smmu->features);
+       dev_info(smmu->dev, "oas %lu-bit (features 0x%08x)\n",
+                smmu->oas, smmu->features);
        return 0;
 }
 
index ae23aacc384029838f0367a14b8fbdb5d2cc0088..0a5bb57dbdfede8d71d98cb6c8640d7278986d1f 100644 (file)
@@ -43,7 +43,6 @@ struct arm_vsmmu;
 #define IDR0_COHACC                    (1 << 4)
 #define IDR0_TTF                       GENMASK(3, 2)
 #define IDR0_TTF_AARCH64               2
-#define IDR0_TTF_AARCH32_64            3
 #define IDR0_S1P                       (1 << 1)
 #define IDR0_S2P                       (1 << 0)
 
@@ -784,7 +783,6 @@ struct arm_smmu_device {
        int                             gerr_irq;
        int                             combined_irq;
 
-       unsigned long                   ias; /* IPA */
        unsigned long                   oas; /* PA */
        unsigned long                   pgsize_bitmap;