KVM: x86: Enforce x2APIC's must-be-zero reserved ICR bits

commit 71bf395a276f0578d19e0ae137a7d1d816d08e0e upstream.

Inject a #GP on a WRMSR(ICR) that attempts to set any reserved bits that
are must-be-zero on both Intel and AMD, i.e. any reserved bits other than
the BUSY bit, which Intel ignores and basically says is undefined.

KVM's xapic_state_test selftest has been fudging the bug since commit
4b88b1a518b3 ("KVM: selftests: Enhance handling WRMSR ICR register in
x2APIC mode"), which essentially removed the testcase instead of fixing
the bug.

WARN if the nodecode path triggers a #GP, as the CPU is supposed to check
reserved bits for ICR when it's partially virtualized.

Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240719235107.3023592-2-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index acd7d48100a1d3360202f33b5fa778b34d38afeb..376fc506740206db5eb75856df129ea42dc5353d 100644 (file)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2470,7 +2470,7 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
         * maybe-unecessary write, and both are in the noise anyways.
         */
        if (apic_x2apic_mode(apic) && offset == APIC_ICR)
-               kvm_x2apic_icr_write(apic, kvm_lapic_get_reg64(apic, APIC_ICR));
+               WARN_ON_ONCE(kvm_x2apic_icr_write(apic, kvm_lapic_get_reg64(apic, APIC_ICR)));
        else
                kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
 }
@@ -3183,8 +3183,21 @@ int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
        return 0;
 }
 
+#define X2APIC_ICR_RESERVED_BITS (GENMASK_ULL(31, 20) | GENMASK_ULL(17, 16) | BIT(13))
+
 int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data)
 {
+       if (data & X2APIC_ICR_RESERVED_BITS)
+               return 1;
+
+       /*
+        * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but
+        * only AMD requires it to be zero, Intel essentially just ignores the
+        * bit.  And if IPI virtualization (Intel) or x2AVIC (AMD) is enabled,
+        * the CPU performs the reserved bits checks, i.e. the underlying CPU
+        * behavior will "win".  Arbitrarily clear the BUSY bit, as there is no
+        * sane way to provide consistent behavior with respect to hardware.
+        */
        data &= ~APIC_ICR_BUSY;
 
        kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32));