This patch makes it so that when you use any of the Cortex-A53 errata
workarounds but have specified an -march or -mcpu we know is not affected by it
that we suppress the errata workaround.
This is a driver only patch as the linker invocation needs to be changed as
well. The linker and cc SPECs are different because for the linker we didn't
seem to add an inversion flag for the option. That said, it's also not possible
to configure the linker with it on by default. So not passing the flag is
sufficient to turn it off.
For the compilers however we have an inversion flag using -mno-, which is needed
to disable the workarounds when the compiler has been configured with it by
default.
In case it's unclear how the patch does what it does (it took me a while to
figure out the syntax):
* Early matching will replace any -march=native or -mcpu=native with their
expanded forms and erases the native arguments from the buffer.
* Due to the above if we ensure we handle the new code after this erasure then
we only have to handle the expanded form.
* The expanded form needs to handle -march=<arch>+extensions and
-mcpu=<cpu>+extensions and so we can't use normal string matching but
instead use strstr with a custom driver function that's common between
native and non-native builds.
* For the compilers we output -mno-<workaround> and for the linker we just
erase the --fix-<workaround> option.
* The extra internal matching, e.g. the duplicate match of mcpu inside:
mcpu=*:%{%:is_local_not_armv8_base(%{mcpu=*:%*}) is so we can extract the glob
using %* because the outer match would otherwise reset at the %{. The reason
for the outer glob at all is to skip the block early if no matches are found.
The workaround has the effect of suppressing certain inlining and multiply-add
formation which leads to about ~1% SPECCPU 2017 Intrate regression on modern
cores. This patch is needed because most distros configure GCC with the
workaround enabled by default.
Expected output:
> gcc -mcpu=neoverse-v1 -mfix-cortex-a53-835769 -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l
0
> gcc -mfix-cortex-a53-835769 -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l
5
> gcc -mfix-cortex-a53-835769 -march=armv8-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l
5
> gcc -mfix-cortex-a53-835769 -march=armv8.1-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-mfix" | wc -l
0
> gcc -mfix-cortex-a53-835769 -march=armv8.1-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-\-fix" | wc -l
0
> gcc -mfix-cortex-a53-835769 -march=armv8-a -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-\-fix" | wc -l
1
> -gcc -mfix-cortex-a53-835769 -xc - -O3 -o - < /dev/null -### 2>&1 | grep "\-\-fix" | wc -l
1
gcc/ChangeLog:
* config/aarch64/aarch64-errata.h (TARGET_SUPPRESS_OPT_SPEC,
TARGET_TURN_OFF_OPT_SPEC, CA53_ERR_835769_COMPILE_SPEC,
CA53_ERR_843419_COMPILE_SPEC): New.
(CA53_ERR_835769_SPEC, CA53_ERR_843419_SPEC): Use them.
* config/aarch64/aarch64-elf-raw.h (CC1_SPEC, CC1PLUS_SPEC): Add
AARCH64_ERRATA_COMPILE_SPEC.
* config/aarch64/aarch64-freebsd.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
* config/aarch64/aarch64-gnu.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
* config/aarch64/aarch64-linux.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
* config/aarch64/aarch64-netbsd.h (CC1_SPEC, CC1PLUS_SPEC): Likewise.
* common/config/aarch64/aarch64-common.cc
(is_host_cpu_not_armv8_base): New.
* config/aarch64/driver-aarch64.cc: Remove extra newline
* config/aarch64/aarch64.h (is_host_cpu_not_armv8_base): New.
(MCPU_TO_MARCH_SPEC_FUNCTIONS): Add is_local_not_armv8_base.
(EXTRA_SPEC_FUNCTIONS): Add is_local_cpu_armv8_base.
* doc/invoke.texi: Document it.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/cpunative/info_30: New test.
* gcc.target/aarch64/cpunative/info_31: New test.
* gcc.target/aarch64/cpunative/info_32: New test.
* gcc.target/aarch64/cpunative/info_33: New test.
* gcc.target/aarch64/cpunative/native_cpu_30.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_31.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_32.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_33.c: New test.
* gcc.target/aarch64/erratas_opt_0.c: New test.
* gcc.target/aarch64/erratas_opt_1.c: New test.
* gcc.target/aarch64/erratas_opt_10.c: New test.
* gcc.target/aarch64/erratas_opt_11.c: New test.
* gcc.target/aarch64/erratas_opt_12.c: New test.
* gcc.target/aarch64/erratas_opt_13.c: New test.
* gcc.target/aarch64/erratas_opt_14.c: New test.
* gcc.target/aarch64/erratas_opt_15.c: New test.
* gcc.target/aarch64/erratas_opt_2.c: New test.
* gcc.target/aarch64/erratas_opt_3.c: New test.
* gcc.target/aarch64/erratas_opt_4.c: New test.
* gcc.target/aarch64/erratas_opt_5.c: New test.
* gcc.target/aarch64/erratas_opt_6.c: New test.
* gcc.target/aarch64/erratas_opt_7.c: New test.
* gcc.target/aarch64/erratas_opt_8.c: New test.
* gcc.target/aarch64/erratas_opt_9.c: New test.
return aarch64_rewrite_selected_cpu (argv[argc - 1]);
}
+/* Checks to see if the host CPU may not be Cortex-A53 or an unknown Armv8-a
+ baseline CPU. */
+
+const char *
+is_host_cpu_not_armv8_base (int argc, const char **argv)
+{
+ gcc_assert (argc);
+
+ /* Default to not knowing what we are if unspecified. The SPEC file should
+ have already mapped configure time options to here through
+ OPTION_DEFAULT_SPECS so we don't need to check the configure variants
+ manually. */
+ if (!argv[0])
+ return NULL;
+
+ const char *res = argv[0];
+
+ /* No SVE system is baseline Armv8-A. */
+ if (strstr (res, "+sve"))
+ return "";
+
+ if (strstr (res, "cortex-a53") || strstr (res, "armv8-a"))
+ return NULL;
+
+ return "";
+}
+
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
#undef AARCH64_CPU_NAME_LENGTH
AARCH64_ERRATA_LINK_SPEC
#endif
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
#endif /* GCC_AARCH64_ELF_RAW_H */
#ifndef GCC_AARCH64_ERRATA_H
#define GCC_AARCH64_ERRATA_H
+/* Completely ignore the option if we've explicitly specify something other than
+ mcpu=cortex-a53 or march=armv8-a. */
+#define TARGET_SUPPRESS_OPT_SPEC(OPT) \
+ "mcpu=*:%{%:is_local_not_armv8_base(%{mcpu=*:%*}):; " OPT \
+ "}; march=*:%{%:is_local_not_armv8_base(%{march=*:%*}):;" OPT "}; " OPT
+
+/* Explicitly turn off the option if we've explicitly specify something other
+ than mcpu=cortex-a53 or march=armv8-a. This will also erase any other usage
+ of the flag making the order of the options not relevant. */
+# define TARGET_TURN_OFF_OPT_SPEC(FLAG) \
+ "mcpu=*:%{%:is_local_not_armv8_base(%{mcpu=*:%*}):%<m" FLAG " -mno-" FLAG \
+ "}; march=*:%{%:is_local_not_armv8_base(%{march=*:%*}):%<m" FLAG " -mno-" FLAG "}"
+
+/* Cortex-A53 835769 Errata. */
+
#if TARGET_FIX_ERR_A53_835769_DEFAULT
-#define CA53_ERR_835769_SPEC \
- " %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}"
+#define CA53_ERR_835769_SPEC \
+ " %{" \
+ TARGET_SUPPRESS_OPT_SPEC ("!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769") \
+ " }"
#else
-#define CA53_ERR_835769_SPEC \
- " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}"
+#define CA53_ERR_835769_SPEC \
+ " %{" \
+ TARGET_SUPPRESS_OPT_SPEC ("mfix-cortex-a53-835769:--fix-cortex-a53-835769") \
+ " }"
#endif
+#define CA53_ERR_835769_COMPILE_SPEC \
+ " %{" TARGET_TURN_OFF_OPT_SPEC ("fix-cortex-a53-835769") "}"
+
+/* Cortex-A53 843419 Errata. */
+
#if TARGET_FIX_ERR_A53_843419_DEFAULT
-#define CA53_ERR_843419_SPEC \
- " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}"
+#define CA53_ERR_843419_SPEC \
+ " %{" \
+ TARGET_SUPPRESS_OPT_SPEC ("!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419") \
+ " }"
#else
-#define CA53_ERR_843419_SPEC \
- " %{mfix-cortex-a53-843419:--fix-cortex-a53-843419}"
+#define CA53_ERR_843419_SPEC \
+ " %{" \
+ TARGET_SUPPRESS_OPT_SPEC ("mfix-cortex-a53-843419:--fix-cortex-a53-843419") \
+ " }"
#endif
+#define CA53_ERR_843419_COMPILE_SPEC \
+ " %{" TARGET_TURN_OFF_OPT_SPEC ("fix-cortex-a53-843419") "}"
+
+/* Exports to use in SPEC files. */
+
#define AARCH64_ERRATA_LINK_SPEC \
CA53_ERR_835769_SPEC \
CA53_ERR_843419_SPEC
+#define AARCH64_ERRATA_COMPILE_SPEC \
+ CA53_ERR_835769_COMPILE_SPEC \
+ CA53_ERR_843419_COMPILE_SPEC
+
#endif /* GCC_AARCH64_ERRATA_H */
-X" SUBTARGET_EXTRA_LINK_SPEC " \
%{mbig-endian:-EB} %{mlittle-endian:-EL}"
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
#undef LINK_SPEC
#define LINK_SPEC FBSD_TARGET_LINK_SPEC AARCH64_ERRATA_LINK_SPEC
%{mbig-endian:-EB} %{mlittle-endian:-EL} \
-maarch64gnu%{mabi=ilp32:32}%{mbig-endian:b}"
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
#define LINK_SPEC GNU_TARGET_LINK_SPEC AARCH64_ERRATA_LINK_SPEC
#undef ASAN_CC1_SPEC
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
-#undef CC1_SPEC
-#define CC1_SPEC GNU_USER_TARGET_CC1_SPEC ASAN_CC1_SPEC
+#undef CC1_SPEC
+#define CC1_SPEC GNU_USER_TARGET_CC1_SPEC ASAN_CC1_SPEC \
+ AARCH64_ERRATA_COMPILE_SPEC
+
+#undef CC1PLUS_SPEC
+#define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
#define CPP_SPEC "%{pthread:-D_REENTRANT}"
"%{mlittle-endian:-EL -m " TARGET_LINKER_LITTLE_EMULATION "} " \
"%(netbsd_link_spec)"
+
+#ifndef CC1_SPEC
+# define CC1_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
+#ifndef CC1PLUS_SPEC
+# define CC1PLUS_SPEC AARCH64_ERRATA_COMPILE_SPEC
+#endif
+
#undef LINK_SPEC
#define LINK_SPEC NETBSD_LINK_SPEC_ELF \
NETBSD_TARGET_LINK_SPEC \
" %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
-#define MCPU_TO_MARCH_SPEC_FUNCTIONS \
- { "rewrite_mcpu", aarch64_rewrite_mcpu },
+extern const char *is_host_cpu_not_armv8_base (int argc, const char **argv);
+#define MCPU_TO_MARCH_SPEC_FUNCTIONS \
+ { "rewrite_mcpu", aarch64_rewrite_mcpu }, \
+ { "is_local_not_armv8_base", is_host_cpu_not_armv8_base },
+
#define ASM_CPU_SPEC \
MCPU_TO_MARCH_SPEC
@itemx -mno-fix-cortex-a53-835769
Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
This involves inserting a NOP instruction between memory instructions and
-64-bit integer multiply-accumulate instructions.
+64-bit integer multiply-accumulate instructions. This flag will be ignored if
+an architecture or cpu is specified on the command line which does not need the
+workaround.
@opindex mfix-cortex-a53-843419
@opindex mno-fix-cortex-a53-843419
@itemx -mno-fix-cortex-a53-843419
Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
This erratum workaround is made at link time and this will only pass the
-corresponding flag to the linker.
+corresponding flag to the linker. This flag will be ignored if
+an architecture or cpu is specified on the command line which does not need the
+workaround.
+
@opindex mlow-precision-recip-sqrt
@opindex mno-low-precision-recip-sqrt
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xd03
+CPU revision : 2
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xfff
+CPU revision : 2
+
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xd03
+CPU revision : 2
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xfff
+CPU revision : 2
+
--- /dev/null
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_30" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Test a normal looking procinfo. */
--- /dev/null
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_31" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Check that an Armv8-A core doesn't fall apart on extensions without midr
+ values and that it enables optional features. */
--- /dev/null
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_32" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Test a normal looking procinfo. */
--- /dev/null
+/* { dg-do link { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_33" } */
+/* { dg-additional-options "-mcpu=native -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
+
+/* Check that an Armv8-A core doesn't fall apart on extensions without midr
+ values and that it enables optional features. */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-843419 -mcpu=neoverse-v1 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv9-a -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-843419 -march=armv9-a -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=cortex-a53 -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv8-a -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -march=armv8-a -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* The input is conflicting, but take cpu over arch. */
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-835769 -mcpu=neoverse-v1 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv9-a -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-835769 -march=armv9-a -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=cortex-a53 -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-march=armv8-a -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -march=armv8-a -mfix-cortex-a53-835769 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* The input is conflicting, but take cpu over arch. */
+/* { dg-message "-mno-fix-cortex-a53-835769" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mcpu=neoverse-v1 -mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mno-fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
--- /dev/null
+/* { dg-do link } */
+/* { dg-additional-options "-mfix-cortex-a53-843419 -###" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-message "-mfix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-message "--fix-cortex-a53-843419" "note" { target *-*-* } 0 } */
+/* { dg-excess-errors "" } */
projects / thirdparty / gcc.git / commitdiff
